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xilinx: add delays to INV

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This commit is contained in:
Eddie Hung
2020-02-27 10:17:29 -08:00
parent 6bb3d9f9c0
commit 3b74e0fa45
1 changed files with 3 additions and 0 deletions
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techlibs/xilinx/cells_sim.v
+3
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@@ -160,6 +160,9 @@ module INV(
input I
);
assign O = !I;
specify
(I => O) = 127;
endspecify
endmodule
(* abc9_lut=1 *)