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https://github.com/YosysHQ/yosys.git
synced 2026-10-06 01:53:53 +02:00
flatten: add -barriers flag
* This uses $barrier optimization barriers to connect wires into the flattened module instead of connections
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@@ -77,6 +77,7 @@ struct FlattenWorker
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bool create_scopeinfo = true;
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bool create_scopename = false;
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std::string separator = ".";
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bool barriers = false;
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template<class T>
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void map_attributes(RTLIL::Cell *cell, T *object, IdString orig_object_name)
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@@ -263,7 +264,27 @@ struct FlattenWorker
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log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n",
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module, cell, port_it.first.unescape(), log_signal(new_conn.first), log_signal(new_conn.second));
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module->connect(new_conn);
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if (barriers) {
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// Drive public output wires with barriers and the rest with
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// connections
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RTLIL::SigSig skip_conn, barrier_conn;
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for (int i = 0; i < GetSize(new_conn.first); i++) {
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const auto lhs = new_conn.first[i], rhs = new_conn.second[i];
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auto& sigsig = !lhs.is_wire() || !lhs.wire->name.isPublic() ? skip_conn : barrier_conn;
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sigsig.first.append(lhs);
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sigsig.second.append(rhs);
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}
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if (!skip_conn.first.empty())
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module->connect(skip_conn);
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if (!barrier_conn.first.empty())
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module->addBarrier(NEW_ID, barrier_conn.second, barrier_conn.first);
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} else {
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module->connect(new_conn);
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}
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sigmap.add(new_conn.first, new_conn.second);
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}
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@@ -369,6 +390,10 @@ struct FlattenPass : public Pass {
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log(" Don't remove unused submodules, leave a flattened version of each\n");
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log(" submodule in the design.\n");
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log("\n");
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log(" -barriers\n");
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log(" Introduce an optimization barrier (a $barrier cell) when a flattened\n");
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log(" module drives a public wire.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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@@ -402,6 +427,9 @@ struct FlattenPass : public Pass {
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}
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if (args[argidx] == "-nocleanup") {
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cleanup = false;
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}
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if (args[argidx] == "-barriers") {
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worker.barriers = true;
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continue;
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}
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break;
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