Don't absorb DSP inputs read elsewhere.

techlibs/lattice/lattice_dsp_nexus.pmg

@@ -64,6 +64,7 @@ pattern nexus_preadd18
 match preadd
 	select preadd->type.in($add, $sub)
 	select GetSize(port(preadd, \Y)) <= 19
+	select nusers(port(preadd, \Y)) == 2
 endmatch
 
 match mul
@@ -76,6 +77,7 @@ endmatch
 match pipe_ff
 	select pipe_ff->type.in($dff, $dffe, $sdff, $sdffe)
 	index <SigBit> port(pipe_ff, \D)[0] === port(mul, \Y)[0]
+	filter nusers(port(mul, \Y)) == 2
 	optional
 endmatch
 
@@ -385,6 +387,7 @@ match ff
 	filter ff->type.in($dff, $dffe) || param(ff, \SRST_VALUE).is_fully_zero()
 	filter GetSize(port(ff, \Q)) == GetSize(argQ)
 	index <SigSpec> port(ff, \Q) === argQ
+	filter nusers(port(ff, \Q)) == 2
 endmatch
 
 code
@@ -422,6 +425,7 @@ match ff
 	filter ff->type.in($dff, $dffe) || param(ff, \SRST_VALUE).is_fully_zero()
 	filter GetSize(port(ff, \D)) == GetSize(argD)
 	index <SigSpec> port(ff, \D) === argD
+	filter nusers(port(ff, \D)) == 2
 endmatch
 
 code

tests/arch/nexus/fuse_mac.sv

@@ -74,3 +74,19 @@ module neg_dot_mixed (input clk, input [8:0] a0,b0,a1,b1, input [17:0] a2, b2, o
 	end
 	assign p = p_r;
 endmodule
+
+// The pre-adder result is also an output
+module preadd_fanout (input [5:0] a, b, d, output [15:0] p, output [6:0] q);
+	assign q = a + d;
+	assign p = q * b;
+endmodule
+
+// The input register is also an output
+module mul_reg_fanout (input clk, input [5:0] a, b, output reg [11:0] y, output [5:0] q);
+	reg [5:0] a_r, b_r;
+	always @(posedge clk) begin
+		a_r <= a; b_r <= b;
+		y <= a_r * b_r;
+	end
+	assign q = a_r;
+endmodule

tests/arch/nexus/fuse_mac.ys

@@ -33,3 +33,14 @@ hierarchy -top neg_dot_mixed;
 synth_nexus -family lifcl -top neg_dot_mixed
 select -assert-count 0 t:MULTADDSUB9X9WIDE
 select -assert-count 2 t:MULTADDSUB18X18
+
+# Cells read elsewhere must not be removed
+design -load pristine
+hierarchy -top preadd_fanout;
+proc
+equiv_opt -assert -map +/lattice/cells_sim_nexus.v synth_nexus -family lifcl -top preadd_fanout -run begin:map_ram
+
+design -load pristine
+hierarchy -top mul_reg_fanout;
+proc
+equiv_opt -assert -map +/lattice/cells_sim_nexus.v synth_nexus -family lifcl -top mul_reg_fanout -run begin:map_ram