luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

abc: remove -lut/-luts

This commit is contained in:
Lofty 2026-03-24 12:59:17 +00:00
parent 5fd39ff3e1
commit 3369cc525f
20 changed files with 35 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

70
passes/techmap/abc.cc
View File

@ -1875,12 +1875,6 @@ struct AbcPass : public Pass {
log(" for -liberty/-genlib with -constr:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR));
log("\n");
log(" for -lut/-luts (only one LUT size):\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack -S 1"));
log("\n");
log(" for -lut/-luts (different LUT sizes):\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT));
log("\n");
log(" for -sop:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP));
log("\n");
@ -1897,9 +1891,6 @@ struct AbcPass : public Pass {
log(" for -liberty/-genlib with -constr:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR));
log("\n");
log(" for -lut/-luts:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT));
log("\n");
log(" for -sop:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP));
log("\n");
@ -1944,26 +1935,9 @@ struct AbcPass : public Pass {
log(" maximum number of SOP products.\n");
log(" (replaces {P} in the default scripts above)\n");
log("\n");
log(" -lut <width>\n");
log(" generate netlist using luts of (max) the specified width.\n");
log("\n");
log(" -lut <w1>:<w2>\n");
log(" generate netlist using luts of (max) the specified width <w2>. All\n");
log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
log(" the area cost doubles with each additional input bit. the delay cost\n");
log(" is still constant for all lut widths.\n");
log("\n");
log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
log(" 2, 3, .. inputs.\n");
log("\n");
log(" -sop\n");
log(" map to sum-of-product cells and inverters\n");
log("\n");
// log(" -mux4, -mux8, -mux16\n");
// log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
// log(" (ignored when used with -liberty/-genlib or -lut)\n");
// log("\n");
log(" -g type1,type2,...\n");
log(" Map to the specified list of gate types. Supported gates types are:\n");
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@ -2136,14 +2110,6 @@ struct AbcPass : public Pass {
config.sop_products = "-P " + args[++argidx];
continue;
}
if (arg == "-lut" && argidx+1 < args.size()) {
lut_arg = args[++argidx];
continue;
}
if (arg == "-luts" && argidx+1 < args.size()) {
luts_arg = args[++argidx];
continue;
}
if (arg == "-sop") {
config.sop_mode = true;
continue;
@ -2225,40 +2191,6 @@ struct AbcPass : public Pass {
if (!config.constr_file.empty() && !is_absolute_path(config.constr_file))
config.constr_file = std::string(pwd) + "/" + config.constr_file;
// handle -lut argument
if (!lut_arg.empty()) {
size_t pos = lut_arg.find_first_of(':');
int lut_mode = 0, lut_mode2 = 0;
if (pos != string::npos) {
lut_mode = atoi(lut_arg.substr(0, pos).c_str());
lut_mode2 = atoi(lut_arg.substr(pos+1).c_str());
} else {
lut_mode = atoi(lut_arg.c_str());
lut_mode2 = lut_mode;
}
config.lut_costs.clear();
for (int i = 0; i < lut_mode; i++)
config.lut_costs.push_back(1);
for (int i = lut_mode; i < lut_mode2; i++)
config.lut_costs.push_back(2 << (i - lut_mode));
}
//handle -luts argument
if (!luts_arg.empty()){
config.lut_costs.clear();
for (auto &tok : split_tokens(luts_arg, ",")) {
auto parts = split_tokens(tok, ":");
if (GetSize(parts) == 0 && !config.lut_costs.empty())
config.lut_costs.push_back(config.lut_costs.back());
else if (GetSize(parts) == 1)
config.lut_costs.push_back(atoi(parts.at(0).c_str()));
else if (GetSize(parts) == 2)
while (GetSize(config.lut_costs) < std::atoi(parts.at(0).c_str()))
config.lut_costs.push_back(atoi(parts.at(1).c_str()));
else
log_cmd_error("Invalid -luts syntax.\n");
}
}
// handle -g argument
if (!g_arg.empty()){
for (auto g : split_tokens(g_arg, ",")) {
@ -2384,8 +2316,6 @@ struct AbcPass : public Pass {
}
}
if (!config.lut_costs.empty() && !(config.liberty_files.empty() && config.genlib_files.empty()))
log_cmd_error("Got -lut and -liberty/-genlib! These two options are exclusive.\n");
if (!config.constr_file.empty() && (config.liberty_files.empty() && config.genlib_files.empty()))
log_cmd_error("Got -constr but no -liberty/-genlib!\n");

4
techlibs/anlogic/synth_anlogic.cc
View File

@ -193,7 +193,7 @@ struct SynthAnlogicPass : public ScriptPass
run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
run("abc9 -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))
@ -206,7 +206,7 @@ struct SynthAnlogicPass : public ScriptPass
if (check_label("map_luts"))
{
run("abc -lut 4:6");
run("abc9 -lut 4:6");
run("clean");
}

2
techlibs/efinix/synth_efinix.cc
View File

@ -196,7 +196,7 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_luts"))
{
run("abc -lut 4");
run("abc9 -lut 4");
run("clean");
}

4
techlibs/gatemate/synth_gatemate.cc
View File

@ -318,11 +318,11 @@ struct SynthGateMatePass : public ScriptPass
run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
}
if (!luttree || help_mode) {
std::string abc_args = " -dress -lut 4";
std::string abc_args = " -lut 4";
if (dff) {
abc_args += " -dff";
}
run("abc " + abc_args, "(without -luttree)");
run("abc9 " + abc_args, "(without -luttree)");
}
run("clean");
}

4
techlibs/lattice/synth_lattice.cc
View File

@ -544,14 +544,14 @@ struct SynthLatticePass : public ScriptPass
abc9_opts += " -dff";
run("abc9" + abc9_opts);
} else {
std::string abc_args = " -dress";
std::string abc_args = "";
if (nowidelut)
abc_args += " -lut 4";
else
abc_args += " -lut " + widelut_abc;
if (dff)
abc_args += " -dff";
run("abc" + abc_args);
run("abc9" + abc_args);
}
run("clean");
}

6
techlibs/nanoxplore/cells_sim.v
View File

@ -10,7 +10,6 @@ assign O = I1 ? s3[1] : s3[0];
endmodule
(* abc9_box, lib_whitebox *)
module NX_DFF(input I, CK, L, R, output reg O);
parameter dff_ctxt = 1'bx;
@ -36,7 +35,6 @@ always @(posedge clock, posedge async_reset)
endmodule
(* abc9_box, lib_whitebox *)
module NX_DFR(input I, CK, L, R, output O);
parameter data_inv = 1'b0;
@ -66,8 +64,6 @@ assign O = data_inv ? O_reg : ~O_reg;
endmodule
(* abc9_box, lib_whitebox *)
module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
parameter add_carry = 0;
@ -175,7 +171,6 @@ module NX_IOB_O(I, C, T, IO);
assign IO = C ? I : 1'bz;
endmodule
(* abc9_box, lib_whitebox *)
module NX_CY_1BIT(CI, A, B, S, CO);
(* abc9_carry *)
input CI;
@ -217,7 +212,6 @@ module NX_BFR(I, O);
assign O = data_inv ? ~I : I;
endmodule
(* abc9_box, lib_whitebox *)
module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3

3
techlibs/nanoxplore/cells_sim_u.v
View File

@ -1,4 +1,3 @@
(* abc9_box, lib_whitebox *)
module NX_GCK_U(SI1, SI2, CMD, SO);
input CMD;
input SI1;
@ -31,7 +30,6 @@ module NX_GCK_U(SI1, SI2, CMD, SO);
assign SO = inv_out ? ~SO_int : SO_int;
endmodule
(* abc9_box, lib_whitebox *)
module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
@ -205,7 +203,6 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
mem[WA] <= I[MEM_WIDTH-1:0];
endmodule
(* abc9_box, lib_whitebox *)
module NX_WFG_U(R, SI, ZI, SO, ZO);
input R;
input SI;

4
techlibs/nanoxplore/synth_nanoxplore.cc
View File

@ -340,9 +340,9 @@ struct SynthNanoXplorePass : public ScriptPass
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
run("abc9" + abc9_opts);
} else {
std::string abc_args = " -dress";
std::string abc_args = "";
abc_args += " -lut 4";
run("abc" + abc_args);
run("abc9" + abc_args);
}
run("techmap -map +/nanoxplore/cells_map.v t:$lut");
run("opt -fast");

4
techlibs/xilinx/synth_xilinx.cc
View File

@ -640,7 +640,7 @@ struct SynthXilinxPass : public ScriptPass
if (flatten_before_abc)
run("flatten");
if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
run("abc9 -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
else if (abc9) {
if (lut_size != 6)
log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n");
@ -681,7 +681,7 @@ struct SynthXilinxPass : public ScriptPass
abc_opts += " -dff";
if (retime)
abc_opts += " -D 1";
run("abc" + abc_opts);
run("abc9" + abc_opts);
}
run("clean");

2
tests/arch/anlogic/mux.ys
View File

@ -27,7 +27,7 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-max 3 t:AL_MAP_LUT3
select -assert-max 3 t:AL_MAP_LUT4
select -assert-max 4 t:AL_MAP_LUT4
select -assert-max 1 t:AL_MAP_LUT5
select -assert-max 1 t:AL_MAP_LUT6

2
tests/arch/efinix/mux.ys
View File

@ -36,6 +36,6 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:EFX_LUT4
select -assert-max 13 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D

2
tests/arch/gatemate/fsm.ys
View File

@ -16,5 +16,5 @@ select -assert-count 1 t:CC_BUFG
select -assert-count 6 t:CC_DFF
select -assert-max 5 t:CC_LUT2
select -assert-max 6 t:CC_LUT3
select -assert-max 9 t:CC_LUT4
select -assert-max 11 t:CC_LUT4
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D

13
tests/arch/gatemate/mux.ys
View File

@ -7,10 +7,8 @@ proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-max 1 t:CC_LUT2
select -assert-max 2 t:CC_LUT4
select -assert-max 1 t:CC_MX2
select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D
select -assert-max 3 t:CC_LUT3
select -assert-none t:CC_LUT3 %% t:* %D
design -load read
hierarchy -top mux8
@ -18,7 +16,6 @@ proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-max 1 t:CC_LUT3
select -assert-max 5 t:CC_LUT4
select -assert-max 1 t:CC_MX2
select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D
select -assert-max 3 t:CC_LUT3
select -assert-max 3 t:CC_LUT4
select -assert-none t:CC_LUT3 t:CC_LUT4 %% t:* %D

2
tests/arch/machxo2/lutram.ys
View File

@ -11,7 +11,7 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite
design -load postopt
cd lutram_1w1r
select -assert-count 20 t:LUT4
select -assert-count 28 t:LUT4
select -assert-count 8 t:TRELLIS_DPR16X4
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D

6
tests/arch/machxo2/mux.ys
View File

@ -15,7 +15,7 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
select -assert-count 3 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
@ -25,7 +25,7 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4
select -assert-count 6 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
@ -35,6 +35,6 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4
select -assert-max 13 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D

2
tests/arch/nexus/counter.ys
View File

@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module
stat
select -assert-count 5 t:CCU2
select -assert-count 8 t:FD1P3DX
select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D
select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:INV t:VLO t:VHI %% t:* %D

5
tests/arch/xilinx/fsm.ys
View File

@ -30,8 +30,7 @@ cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 1 t:LUT1
select -assert-max 1 t:LUT3
select -assert-max 6 t:LUT3
select -assert-max 8 t:LUT4
select -assert-count 5 t:MUXF5
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:MUXF5 %% t:* %D

5
tests/arch/xilinx/macc.ys
View File

@ -27,6 +27,5 @@ cd macc2 # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 1 t:FDRE
select -assert-count 1 t:LUT2
select -assert-count 40 t:LUT3
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D
select -assert-count 41 t:LUT2
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 %% t:* %D

11
tests/arch/xilinx/mux_lut4.ys
View File

@ -32,11 +32,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux8 # Constrain all select calls below inside the top module
select -assert-max 5 t:LUT1
select -assert-max 3 t:LUT3
select -assert-max 3 t:LUT4
select -assert-max 5 t:LUT4
select -assert-max 3 t:MUXF5
select -assert-count 1 t:MUXF6
select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D
select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
design -load read
@ -45,8 +44,10 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 32 t:LUT*
select -assert-max 34 t:LUT*
select -assert-max 16 t:MUXF5
select -assert-max 8 t:MUXF6
select -assert-max 4 t:MUXF7
select -assert-max 1 t:MUXF8
select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 %% t:* %D
select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 t:MUXF8 %% t:* %D

2
tests/techmap/shiftx2mux.ys
View File

@ -75,7 +75,7 @@ design -save gold
design -load gold
techmap
abc -lut 6
abc9 -lut 6
select -assert-count 16 t:$lut
design -stash gate