diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index d58f6b355..686a907d5 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1875,12 +1875,6 @@ struct AbcPass : public Pass { log(" for -liberty/-genlib with -constr:\n"); log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR)); log("\n"); - log(" for -lut/-luts (only one LUT size):\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack -S 1")); - log("\n"); - log(" for -lut/-luts (different LUT sizes):\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT)); - log("\n"); log(" for -sop:\n"); log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP)); log("\n"); @@ -1897,9 +1891,6 @@ struct AbcPass : public Pass { log(" for -liberty/-genlib with -constr:\n"); log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR)); log("\n"); - log(" for -lut/-luts:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT)); - log("\n"); log(" for -sop:\n"); log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP)); log("\n"); @@ -1944,26 +1935,9 @@ struct AbcPass : public Pass { log(" maximum number of SOP products.\n"); log(" (replaces {P} in the default scripts above)\n"); log("\n"); - log(" -lut \n"); - log(" generate netlist using luts of (max) the specified width.\n"); - log("\n"); - log(" -lut :\n"); - log(" generate netlist using luts of (max) the specified width . All\n"); - log(" luts with width <= have constant cost. for luts larger than \n"); - log(" the area cost doubles with each additional input bit. the delay cost\n"); - log(" is still constant for all lut widths.\n"); - log("\n"); - log(" -luts ,,,:,..\n"); - log(" generate netlist using luts. Use the specified costs for luts with 1,\n"); - log(" 2, 3, .. inputs.\n"); - log("\n"); log(" -sop\n"); log(" map to sum-of-product cells and inverters\n"); log("\n"); - // log(" -mux4, -mux8, -mux16\n"); - // log(" try to extract 4-input, 8-input, and/or 16-input muxes\n"); - // log(" (ignored when used with -liberty/-genlib or -lut)\n"); - // log("\n"); log(" -g type1,type2,...\n"); log(" Map to the specified list of gate types. Supported gates types are:\n"); // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -2136,14 +2110,6 @@ struct AbcPass : public Pass { config.sop_products = "-P " + args[++argidx]; continue; } - if (arg == "-lut" && argidx+1 < args.size()) { - lut_arg = args[++argidx]; - continue; - } - if (arg == "-luts" && argidx+1 < args.size()) { - luts_arg = args[++argidx]; - continue; - } if (arg == "-sop") { config.sop_mode = true; continue; @@ -2225,40 +2191,6 @@ struct AbcPass : public Pass { if (!config.constr_file.empty() && !is_absolute_path(config.constr_file)) config.constr_file = std::string(pwd) + "/" + config.constr_file; - // handle -lut argument - if (!lut_arg.empty()) { - size_t pos = lut_arg.find_first_of(':'); - int lut_mode = 0, lut_mode2 = 0; - if (pos != string::npos) { - lut_mode = atoi(lut_arg.substr(0, pos).c_str()); - lut_mode2 = atoi(lut_arg.substr(pos+1).c_str()); - } else { - lut_mode = atoi(lut_arg.c_str()); - lut_mode2 = lut_mode; - } - config.lut_costs.clear(); - for (int i = 0; i < lut_mode; i++) - config.lut_costs.push_back(1); - for (int i = lut_mode; i < lut_mode2; i++) - config.lut_costs.push_back(2 << (i - lut_mode)); - } - //handle -luts argument - if (!luts_arg.empty()){ - config.lut_costs.clear(); - for (auto &tok : split_tokens(luts_arg, ",")) { - auto parts = split_tokens(tok, ":"); - if (GetSize(parts) == 0 && !config.lut_costs.empty()) - config.lut_costs.push_back(config.lut_costs.back()); - else if (GetSize(parts) == 1) - config.lut_costs.push_back(atoi(parts.at(0).c_str())); - else if (GetSize(parts) == 2) - while (GetSize(config.lut_costs) < std::atoi(parts.at(0).c_str())) - config.lut_costs.push_back(atoi(parts.at(1).c_str())); - else - log_cmd_error("Invalid -luts syntax.\n"); - } - } - // handle -g argument if (!g_arg.empty()){ for (auto g : split_tokens(g_arg, ",")) { @@ -2384,8 +2316,6 @@ struct AbcPass : public Pass { } } - if (!config.lut_costs.empty() && !(config.liberty_files.empty() && config.genlib_files.empty())) - log_cmd_error("Got -lut and -liberty/-genlib! These two options are exclusive.\n"); if (!config.constr_file.empty() && (config.liberty_files.empty() && config.genlib_files.empty())) log_cmd_error("Got -constr but no -liberty/-genlib!\n"); diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index a03374fb0..61057f0ca 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -193,7 +193,7 @@ struct SynthAnlogicPass : public ScriptPass run("techmap -map +/techmap.v -map +/anlogic/arith_map.v"); run("opt -fast"); if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); + run("abc9 -dff -D 1", "(only if -retime)"); } if (check_label("map_ffs")) @@ -206,7 +206,7 @@ struct SynthAnlogicPass : public ScriptPass if (check_label("map_luts")) { - run("abc -lut 4:6"); + run("abc9 -lut 4:6"); run("clean"); } diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index ef245e755..b6b04992a 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -196,7 +196,7 @@ struct SynthEfinixPass : public ScriptPass if (check_label("map_luts")) { - run("abc -lut 4"); + run("abc9 -lut 4"); run("clean"); } diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index 7726e7a15..d890f8ca1 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -318,11 +318,11 @@ struct SynthGateMatePass : public ScriptPass run("techmap -map +/gatemate/inv_map.v", "(with -luttree)"); } if (!luttree || help_mode) { - std::string abc_args = " -dress -lut 4"; + std::string abc_args = " -lut 4"; if (dff) { abc_args += " -dff"; } - run("abc " + abc_args, "(without -luttree)"); + run("abc9 " + abc_args, "(without -luttree)"); } run("clean"); } diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index 744beb650..1437734b4 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -544,14 +544,14 @@ struct SynthLatticePass : public ScriptPass abc9_opts += " -dff"; run("abc9" + abc9_opts); } else { - std::string abc_args = " -dress"; + std::string abc_args = ""; if (nowidelut) abc_args += " -lut 4"; else abc_args += " -lut " + widelut_abc; if (dff) abc_args += " -dff"; - run("abc" + abc_args); + run("abc9" + abc_args); } run("clean"); } diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 7453821d0..e771ffdaf 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -10,7 +10,6 @@ assign O = I1 ? s3[1] : s3[0]; endmodule -(* abc9_box, lib_whitebox *) module NX_DFF(input I, CK, L, R, output reg O); parameter dff_ctxt = 1'bx; @@ -36,7 +35,6 @@ always @(posedge clock, posedge async_reset) endmodule -(* abc9_box, lib_whitebox *) module NX_DFR(input I, CK, L, R, output O); parameter data_inv = 1'b0; @@ -66,8 +64,6 @@ assign O = data_inv ? O_reg : ~O_reg; endmodule - -(* abc9_box, lib_whitebox *) module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO); parameter add_carry = 0; @@ -175,7 +171,6 @@ module NX_IOB_O(I, C, T, IO); assign IO = C ? I : 1'bz; endmodule -(* abc9_box, lib_whitebox *) module NX_CY_1BIT(CI, A, B, S, CO); (* abc9_carry *) input CI; @@ -217,7 +212,6 @@ module NX_BFR(I, O); assign O = data_inv ? ~I : I; endmodule -(* abc9_box, lib_whitebox *) module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 , AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10 , BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3 diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index e11aaabee..3e544a757 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -1,4 +1,3 @@ -(* abc9_box, lib_whitebox *) module NX_GCK_U(SI1, SI2, CMD, SO); input CMD; input SI1; @@ -31,7 +30,6 @@ module NX_GCK_U(SI1, SI2, CMD, SO); assign SO = inv_out ? ~SO_int : SO_int; endmodule -(* abc9_box, lib_whitebox *) module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20 , I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5 , O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26 @@ -205,7 +203,6 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 mem[WA] <= I[MEM_WIDTH-1:0]; endmodule -(* abc9_box, lib_whitebox *) module NX_WFG_U(R, SI, ZI, SO, ZO); input R; input SI; diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 3445ea1be..557eb7ef7 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -340,9 +340,9 @@ struct SynthNanoXplorePass : public ScriptPass abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); run("abc9" + abc9_opts); } else { - std::string abc_args = " -dress"; + std::string abc_args = ""; abc_args += " -lut 4"; - run("abc" + abc_args); + run("abc9" + abc_args); } run("techmap -map +/nanoxplore/cells_map.v t:$lut"); run("opt -fast"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c487206db..d9182a9dc 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -640,7 +640,7 @@ struct SynthXilinxPass : public ScriptPass if (flatten_before_abc) run("flatten"); if (help_mode) - run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')"); + run("abc9 -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')"); else if (abc9) { if (lut_size != 6) log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n"); @@ -681,7 +681,7 @@ struct SynthXilinxPass : public ScriptPass abc_opts += " -dff"; if (retime) abc_opts += " -D 1"; - run("abc" + abc_opts); + run("abc9" + abc_opts); } run("clean"); diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys index 64a04d08d..3508cf56b 100644 --- a/tests/arch/anlogic/mux.ys +++ b/tests/arch/anlogic/mux.ys @@ -27,7 +27,7 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-max 3 t:AL_MAP_LUT3 -select -assert-max 3 t:AL_MAP_LUT4 +select -assert-max 4 t:AL_MAP_LUT4 select -assert-max 1 t:AL_MAP_LUT5 select -assert-max 1 t:AL_MAP_LUT6 diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys index 67006b6f2..4fa67c49b 100644 --- a/tests/arch/efinix/mux.ys +++ b/tests/arch/efinix/mux.ys @@ -36,6 +36,6 @@ proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-max 12 t:EFX_LUT4 +select -assert-max 13 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys index 506862c90..f19b77c18 100644 --- a/tests/arch/gatemate/fsm.ys +++ b/tests/arch/gatemate/fsm.ys @@ -16,5 +16,5 @@ select -assert-count 1 t:CC_BUFG select -assert-count 6 t:CC_DFF select -assert-max 5 t:CC_LUT2 select -assert-max 6 t:CC_LUT3 -select -assert-max 9 t:CC_LUT4 +select -assert-max 11 t:CC_LUT4 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D diff --git a/tests/arch/gatemate/mux.ys b/tests/arch/gatemate/mux.ys index 320ff33d7..b02a24476 100644 --- a/tests/arch/gatemate/mux.ys +++ b/tests/arch/gatemate/mux.ys @@ -7,10 +7,8 @@ proc equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-max 1 t:CC_LUT2 -select -assert-max 2 t:CC_LUT4 -select -assert-max 1 t:CC_MX2 -select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D +select -assert-max 3 t:CC_LUT3 +select -assert-none t:CC_LUT3 %% t:* %D design -load read hierarchy -top mux8 @@ -18,7 +16,6 @@ proc equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-max 1 t:CC_LUT3 -select -assert-max 5 t:CC_LUT4 -select -assert-max 1 t:CC_MX2 -select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D +select -assert-max 3 t:CC_LUT3 +select -assert-max 3 t:CC_LUT4 +select -assert-none t:CC_LUT3 t:CC_LUT4 %% t:* %D diff --git a/tests/arch/machxo2/lutram.ys b/tests/arch/machxo2/lutram.ys index 65af7b2c2..34c95909c 100644 --- a/tests/arch/machxo2/lutram.ys +++ b/tests/arch/machxo2/lutram.ys @@ -11,7 +11,7 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r -select -assert-count 20 t:LUT4 +select -assert-count 28 t:LUT4 select -assert-count 8 t:TRELLIS_DPR16X4 select -assert-count 8 t:TRELLIS_FF select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 6d4e10dc7..c2e636008 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -15,7 +15,7 @@ proc equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:LUT4 +select -assert-count 3 t:LUT4 select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D @@ -25,7 +25,7 @@ proc equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT4 +select -assert-count 6 t:LUT4 select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D @@ -35,6 +35,6 @@ proc equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-max 12 t:LUT4 +select -assert-max 13 t:LUT4 select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/nexus/counter.ys b/tests/arch/nexus/counter.ys index 44421e377..87fe76765 100644 --- a/tests/arch/nexus/counter.ys +++ b/tests/arch/nexus/counter.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module stat select -assert-count 5 t:CCU2 select -assert-count 8 t:FD1P3DX -select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D +select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:INV t:VLO t:VHI %% t:* %D diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 3b1919627..5890049ef 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -30,8 +30,7 @@ cd fsm # Constrain all select calls below inside the top module stat select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE -select -assert-count 1 t:LUT1 -select -assert-max 1 t:LUT3 +select -assert-max 6 t:LUT3 select -assert-max 8 t:LUT4 select -assert-count 5 t:MUXF5 -select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D +select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:MUXF5 %% t:* %D diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 61a570f48..3ff31c1c1 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -27,6 +27,5 @@ cd macc2 # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 1 t:FDRE -select -assert-count 1 t:LUT2 -select -assert-count 40 t:LUT3 -select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D +select -assert-count 41 t:LUT2 +select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 %% t:* %D diff --git a/tests/arch/xilinx/mux_lut4.ys b/tests/arch/xilinx/mux_lut4.ys index 147601dce..9ee6051ee 100644 --- a/tests/arch/xilinx/mux_lut4.ys +++ b/tests/arch/xilinx/mux_lut4.ys @@ -32,11 +32,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux8 # Constrain all select calls below inside the top module select -assert-max 5 t:LUT1 select -assert-max 3 t:LUT3 -select -assert-max 3 t:LUT4 +select -assert-max 5 t:LUT4 select -assert-max 3 t:MUXF5 -select -assert-count 1 t:MUXF6 -select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D +select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D design -load read @@ -45,8 +44,10 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-max 32 t:LUT* +select -assert-max 34 t:LUT* +select -assert-max 16 t:MUXF5 select -assert-max 8 t:MUXF6 select -assert-max 4 t:MUXF7 +select -assert-max 1 t:MUXF8 -select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 %% t:* %D +select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys index 680681297..5d0aedf5a 100644 --- a/tests/techmap/shiftx2mux.ys +++ b/tests/techmap/shiftx2mux.ys @@ -75,7 +75,7 @@ design -save gold design -load gold techmap -abc -lut 6 +abc9 -lut 6 select -assert-count 16 t:$lut design -stash gate