mirror of https://github.com/YosysHQ/yosys.git
further cleanup
This commit is contained in:
Lofty
parent
3369cc525f
commit
1f024ca1ed
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@ -31,13 +31,11 @@
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#define ABC_COMMAND_LIB "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
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#define ABC_COMMAND_CTR "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_COMMAND_LUT "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; dch -f; if; mfs2"
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#define ABC_COMMAND_SOP "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
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#define ABC_COMMAND_DFL "strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
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#define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
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#define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
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#define ABC_FAST_COMMAND_LUT "strash; dretime; if"
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#define ABC_FAST_COMMAND_SOP "strash; dretime; cover {I} {P}"
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#define ABC_FAST_COMMAND_DFL "strash; dretime; map"
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@ -125,7 +123,6 @@ struct AbcConfig
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std::vector<std::string> liberty_files;
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std::vector<std::string> genlib_files;
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std::string constr_file;
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vector<int> lut_costs;
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std::string delay_target;
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std::string sop_inputs;
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std::string sop_products;
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@ -135,7 +132,6 @@ struct AbcConfig
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bool fast_mode = false;
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bool show_tempdir = false;
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bool sop_mode = false;
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bool abc_dress = false;
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bool map_mux4 = false;
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bool map_mux8 = false;
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bool map_mux16 = false;
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@ -1031,9 +1027,6 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
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if (!config.constr_file.empty())
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abc_script += stringf("read_constr -v \"%s\"; ", config.constr_file);
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} else
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if (!config.lut_costs.empty())
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abc_script += stringf("read_lut %s/lutdefs.txt; ", config.global_tempdir_name);
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else
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abc_script += stringf("read_library %s/stdcells.genlib; ", config.global_tempdir_name);
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if (!config.script_file.empty()) {
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@ -1048,14 +1041,6 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
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abc_script += script_file[i];
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} else
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abc_script += stringf("source %s", script_file);
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} else if (!config.lut_costs.empty()) {
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bool all_luts_cost_same = true;
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for (int this_cost : config.lut_costs)
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if (this_cost != config.lut_costs.front())
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all_luts_cost_same = false;
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abc_script += config.fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
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if (all_luts_cost_same && !config.fast_mode)
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abc_script += "; lutpack -S 1";
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} else if (!config.liberty_files.empty() || !config.genlib_files.empty())
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abc_script += config.constr_file.empty() ?
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(config.fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (config.fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
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@ -1077,8 +1062,6 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
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for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{P}", pos))
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abc_script = abc_script.substr(0, pos) + config.sop_products + abc_script.substr(pos+3);
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if (config.abc_dress)
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abc_script += stringf("; dress \"%s/input.blif\"", run_abc.per_run_tempdir_name);
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abc_script += stringf("; write_blif %s/output.blif", run_abc.per_run_tempdir_name);
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abc_script = add_echos_to_abc_cmd(abc_script);
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#if defined(REUSE_YOSYS_ABC_PROCESSES)
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@ -1440,61 +1423,51 @@ void RunAbcState::run(ConcurrentStack<AbcProcess> &)
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void emit_global_input_files(const AbcConfig &config)
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{
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if (!config.lut_costs.empty()) {
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std::string buffer = stringf("%s/lutdefs.txt", config.global_tempdir_name.c_str());
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FILE *f = fopen(buffer.c_str(), "wt");
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if (f == nullptr)
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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for (int i = 0; i < GetSize(config.lut_costs); i++)
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fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i));
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fclose(f);
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} else {
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auto &cell_cost = config.cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
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auto &cell_cost = config.cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
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std::string buffer = stringf("%s/stdcells.genlib", config.global_tempdir_name.c_str());
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FILE *f = fopen(buffer.c_str(), "wt");
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if (f == nullptr)
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
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fprintf(f, "GATE ONE 1 Y=CONST1;\n");
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fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
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fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
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if (config.enabled_gates.count("AND"))
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fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
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if (config.enabled_gates.count("NAND"))
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fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
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if (config.enabled_gates.count("OR"))
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fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
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if (config.enabled_gates.count("NOR"))
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fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
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if (config.enabled_gates.count("XOR"))
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fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
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if (config.enabled_gates.count("XNOR"))
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fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
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if (config.enabled_gates.count("ANDNOT"))
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fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
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if (config.enabled_gates.count("ORNOT"))
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fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
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if (config.enabled_gates.count("AOI3"))
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fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
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if (config.enabled_gates.count("OAI3"))
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fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
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if (config.enabled_gates.count("AOI4"))
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fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
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if (config.enabled_gates.count("OAI4"))
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fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
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if (config.enabled_gates.count("MUX"))
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fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
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if (config.enabled_gates.count("NMUX"))
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fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
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if (config.map_mux4)
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fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
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if (config.map_mux8)
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fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
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if (config.map_mux16)
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fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
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fclose(f);
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}
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std::string buffer = stringf("%s/stdcells.genlib", config.global_tempdir_name.c_str());
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FILE *f = fopen(buffer.c_str(), "wt");
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if (f == nullptr)
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log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
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fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
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fprintf(f, "GATE ONE 1 Y=CONST1;\n");
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fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
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fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
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if (config.enabled_gates.count("AND"))
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fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
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if (config.enabled_gates.count("NAND"))
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fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
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if (config.enabled_gates.count("OR"))
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fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
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if (config.enabled_gates.count("NOR"))
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fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
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if (config.enabled_gates.count("XOR"))
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fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
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if (config.enabled_gates.count("XNOR"))
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fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
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if (config.enabled_gates.count("ANDNOT"))
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fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
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if (config.enabled_gates.count("ORNOT"))
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fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
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if (config.enabled_gates.count("AOI3"))
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fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
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if (config.enabled_gates.count("OAI3"))
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fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
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if (config.enabled_gates.count("AOI4"))
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fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
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if (config.enabled_gates.count("OAI4"))
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fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
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if (config.enabled_gates.count("MUX"))
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fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
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if (config.enabled_gates.count("NMUX"))
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fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
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if (config.map_mux4)
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fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
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if (config.map_mux8)
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fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
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if (config.map_mux16)
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fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
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fclose(f);
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}
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void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module)
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@ -1730,13 +1703,6 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
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continue;
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}
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if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
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SigSpec my_a = module->wire(remap_name(c->getPort(ID::A).as_wire()->name));
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SigSpec my_y = module->wire(remap_name(c->getPort(ID::Y).as_wire()->name));
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connect(assign_map, module, RTLIL::SigSig(my_a, my_y));
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continue;
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}
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RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
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if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
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cell->parameters = c->parameters;
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@ -1988,11 +1954,6 @@ struct AbcPass : public Pass {
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log(" this attribute is a unique integer for each ABC process started. This\n");
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log(" is useful for debugging the partitioning of clock domains.\n");
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log("\n");
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log(" -dress\n");
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log(" run the 'dress' command after all other ABC commands. This aims to\n");
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log(" preserve naming by an equivalence check between the original and\n");
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log(" post-ABC netlists (experimental).\n");
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log("\n");
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log("When no target cell library is specified the Yosys standard cell library is\n");
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log("loaded into ABC before the ABC script is executed.\n");
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log("\n");
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@ -2014,7 +1975,7 @@ struct AbcPass : public Pass {
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AbcConfig config;
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// get arguments from scratchpad first, then override by command arguments
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std::string lut_arg, luts_arg, g_arg;
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std::string g_arg;
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config.exe_file = design->scratchpad_get_string("abc.exe", yosys_abc_executable /* inherit default value if not set */);
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config.script_file = design->scratchpad_get_string("abc.script", "");
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std::string default_liberty_file = design->scratchpad_get_string("abc.liberty", "");
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@ -2028,13 +1989,10 @@ struct AbcPass : public Pass {
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if (design->scratchpad.count("abc.P")) {
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config.sop_products = "-P " + design->scratchpad_get_string("abc.P");
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}
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lut_arg = design->scratchpad_get_string("abc.lut", lut_arg);
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luts_arg = design->scratchpad_get_string("abc.luts", luts_arg);
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config.sop_mode = design->scratchpad_get_bool("abc.sop", false);
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config.map_mux4 = design->scratchpad_get_bool("abc.mux4", false);
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config.map_mux8 = design->scratchpad_get_bool("abc.mux8", false);
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config.map_mux16 = design->scratchpad_get_bool("abc.mux16", false);
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config.abc_dress = design->scratchpad_get_bool("abc.dress", false);
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g_arg = design->scratchpad_get_string("abc.g", g_arg);
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config.fast_mode = design->scratchpad_get_bool("abc.fast", false);
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@ -2126,10 +2084,6 @@ struct AbcPass : public Pass {
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config.map_mux16 = true;
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continue;
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}
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if (arg == "-dress") {
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config.abc_dress = true;
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continue;
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}
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if (arg == "-g" && argidx+1 < args.size()) {
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if (g_arg_from_cmd)
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log_cmd_error("Can only use -g once. Please combine.");
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