luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

misc: review feedback, remove MUL vestiges

This commit is contained in:
Mohamed Gaber 2025-05-15 18:01:13 +03:00
parent 46ba89059a
commit 1d9fbb6143
2 changed files with 3 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/silimate/splitlarge.cc
View File

@ -58,8 +58,6 @@
auto width_low = width / 2; auto width_low = width / 2;
auto width_high = width - width_low; // Handle odd widths auto width_high = width - width_low; // Handle odd widths
auto a = cell->getPort(ID::A);
auto b = cell->getPort(ID::B);
bool aSigned = cell->parameters[ID::A_SIGNED].as_bool(); bool aSigned = cell->parameters[ID::A_SIGNED].as_bool();
bool bSigned = cell->parameters[ID::B_SIGNED].as_bool(); bool bSigned = cell->parameters[ID::B_SIGNED].as_bool();
SigSpec aHigh, aLow, bHigh, bLow; SigSpec aHigh, aLow, bHigh, bLow;
@ -198,6 +196,6 @@
Pass::call(design, "clean *"); Pass::call(design, "clean *");
} }
} SplitfanoutPass; } SplitlargePass;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END

9
tests/silimate/wide_op.v
View File

@ -4,11 +4,10 @@
); );
parameter width = 1024; parameter width = 1024;
// ADD/SUB: 0/4 + (0 unsigned+unsigned, 1 unsigned+signed, 2 signed+unsigned, 3 signed+signed) // ADD/SUB: 0/4 + (0 unsigned;unsigned, 1 unsigned;signed, 2 signed;unsigned, 3 signed;signed)
// reserved for MUL: 8
parameter op = 0; parameter op = 0;
localparam ywidth = (op == 8) ? width * 2 : width; localparam ywidth = width; // (op == MUL) ? width * 2 : width;
input[width-1:0] a; input[width-1:0] a;
input[width-1:0] b; input[width-1:0] b;
output [width-1:0] y; output [width-1:0] y;
@ -31,9 +30,5 @@
assign {c, y} = $signed(a) - b; assign {c, y} = $signed(a) - b;
else if (op == 7) else if (op == 7)
assign {c, y} = $signed(a) - $signed(b); assign {c, y} = $signed(a) - $signed(b);
else if (op == 8) begin
assign c = 0;
assign y = a * b;
end
endgenerate endgenerate
endmodule endmodule