mirror of https://github.com/YosysHQ/yosys.git
78 lines
1.5 KiB
Plaintext
78 lines
1.5 KiB
Plaintext
log -header "Simple positive case with 4-long mux chain and 1 inverted component"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] s,
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input wire [3:0] b,
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input wire a,
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output wire y
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);
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assign y = s[0] ? b[0] : (s[1] ? b[1] : ~(s[2] ? b[2] : (s[3] ? b[3] : a)));
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$mux
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select -assert-count 3 t:$not
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple negative case with 4-long mux chain and 1 inverted fo2 component"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] s,
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input wire [3:0] b,
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input wire a,
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output wire y,
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output wire y2
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);
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wire m;
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assign m = s[2] ? b[2] : (s[3] ? b[3] : a);
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assign y2 = m;
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assign y = s[0] ? b[0] : (s[1] ? b[1] : ~m);
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$mux
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select -assert-count 1 t:$not
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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