mirror of https://github.com/YosysHQ/yosys.git
Make SigSpec::is_fully_ones use chunk iterator
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@ -5464,12 +5464,11 @@ bool RTLIL::SigSpec::is_fully_ones() const
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{
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cover("kernel.rtlil.sigspec.is_fully_ones");
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pack();
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for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
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if (it->width > 0 && it->wire != NULL)
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for (auto &chunk : chunks()) {
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if (chunk.width > 0 && chunk.wire != NULL)
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return false;
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for (size_t i = 0; i < it->data.size(); i++)
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if (it->data[i] != RTLIL::State::S1)
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for (RTLIL::State d : chunk.data)
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if (d != RTLIL::State::S1)
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return false;
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}
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return true;
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