luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

rtlil: simplify extract for performance

This commit is contained in:
Emil J. Tywoniak 2026-04-23 13:58:20 +02:00
parent 3ccbd38cc6
commit 14b0efeced
1 changed files with 3 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
kernel/rtlil.cc
View File

@ -5272,25 +5272,9 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
log_assert(length >= 0);
log_assert(offset + length <= size());
SigSpec extracted;
Chunks cs = chunks();
auto it = cs.begin();
for (; offset; offset -= it->width, ++it) {
if (offset < it->width) {
int chunk_length = min(it->width - offset, length);
extracted.append(it->extract(offset, chunk_length));
length -= chunk_length;
++it;
break;
}
}
for (; length; length -= it->width, ++it) {
if (length >= it->width) {
extracted.append(*it);
} else {
extracted.append(it->extract(0, length));
break;
}
std::vector<SigBit> extracted;
for (int i = offset; i < offset + length; i++) {
extracted.push_back((*this)[i]);
}
return extracted;
}