mirror of https://github.com/YosysHQ/yosys.git
added extra test for muxes
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@ -485,7 +485,7 @@ design -reset
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log -pop
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# TODO
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log -header "MUX chain with multiple branches"
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log -push
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design -reset
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@ -520,6 +520,51 @@ log -pop
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log -header "MUX chain with multiple uneven branches"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [5:0] sel,
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input wire [6:0] a,
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output wire x
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);
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wire w1, w2, w3, w4, w5;
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assign w1 = sel[0] ? a[1] : a[0];
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assign w2 = sel[1] ? a[2] : w1;
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assign w3 = sel[2] ? a[3] : w2;
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assign w4 = sel[3] ? w3 : w5;
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assign w5 = sel[5] ? a[4] : a[5];
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assign x = sel[4] ? w4 : a[6];
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endmodule
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EOF
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check -assert
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autoname
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write_json dump_pre.json
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exec -- netlistsvg dump_pre.json -o dump_pre.svg
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# Check equivalence after extract_reduce
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equiv_opt -assert extract_reduce
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# Load design and run opt_clean to remove unnecessary wires
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design -load postopt
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opt_clean
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autoname
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write_json dump_post.json
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exec -- netlistsvg dump_post.json -o dump_post.svg
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# Check we got a single pmux
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select -assert-count 0 t:$mux
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select -assert-count 1 t:$pmux
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design -reset
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log -pop
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log -header "No off-chain MUX chain"
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log -push
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design -reset
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