diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index f7e2b53b5..9fa45b2a8 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -342,7 +342,7 @@ struct Abc9Pass : public ScriptPass
 		}
 
 		if (check_label("pre")) {
-			run("read_verilog -icells -lib -specify +/abc9_model.v");
+			run("read_techlib -icells -lib -specify +/abc9_model.v");
 			if (help_mode)
 				run("abc9_ops -break_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
 			else
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 984926be8..f3a81ca6d 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1149,7 +1149,7 @@ struct TechmapPass : public Pass {
 
 		std::vector<std::string> map_files;
 		std::vector<RTLIL::IdString> dont_map;
-		std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells";
+		std::string techlib_frontend = "techlib -nooverwrite -noblackbox -icells";
 		int max_iter = -1;
 
 		size_t argidx;
@@ -1163,15 +1163,15 @@ struct TechmapPass : public Pass {
 				continue;
 			}
 			if (args[argidx] == "-D" && argidx+1 < args.size()) {
-				verilog_frontend += " -D " + args[++argidx];
+				techlib_frontend += " -D " + args[++argidx];
 				continue;
 			}
 			if (args[argidx] == "-I" && argidx+1 < args.size()) {
-				verilog_frontend += " -I " + args[++argidx];
+				techlib_frontend += " -I " + args[++argidx];
 				continue;
 			}
 			if (args[argidx] == "-relativeshare") {
-				verilog_frontend += " -relativeshare";
+				techlib_frontend += " -relativeshare";
 				log_experimental("techmap -relativeshare");
 				continue;
 			}
@@ -1205,7 +1205,7 @@ struct TechmapPass : public Pass {
 
 		RTLIL::Design *map = new RTLIL::Design;
 		if (map_files.empty()) {
-			Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend);
+			Frontend::frontend_call(map, nullptr, "+/techmap.v", techlib_frontend);
 		} else {
 			for (auto &fn : map_files)
 				if (fn.compare(0, 1, "%") == 0) {
@@ -1217,7 +1217,7 @@ struct TechmapPass : public Pass {
 						if (!map->module(mod->name))
 							map->add(mod->clone());
 				} else {
-					Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));
+					Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : techlib_frontend));
 				}
 		}
 
diff --git a/techlibs/achronix/CMakeLists.txt b/techlibs/achronix/CMakeLists.txt
index 5fa7402e7..73a1ca901 100644
--- a/techlibs/achronix/CMakeLists.txt
+++ b/techlibs/achronix/CMakeLists.txt
@@ -13,7 +13,7 @@ yosys_pass(synth_achronix
 		memory_map
 		opt
 		proc
-		read_verilog
+		read_techlib
 		setundef
 		stat
 		synth
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index f8993de91..053c00f86 100644
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -122,7 +122,7 @@ struct SynthAchronixPass : public ScriptPass {
   {
     if (check_label("begin"))
       {
-        run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
+        run("read_techlib -sv -lib +/achronix/speedster22i/cells_sim.v");
         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
       }
 
diff --git a/techlibs/analogdevices/CMakeLists.txt b/techlibs/analogdevices/CMakeLists.txt
index 34962f7f8..791aa55b0 100644
--- a/techlibs/analogdevices/CMakeLists.txt
+++ b/techlibs/analogdevices/CMakeLists.txt
@@ -27,7 +27,7 @@ yosys_pass(synth_analogdevices
 		peepopt
 		pmux2shiftx
 		proc
-		read_verilog
+		read_techlib
 		select
 		setattr
 		share
diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc
index aa27c78b6..ee589ac87 100644
--- a/techlibs/analogdevices/synth_analogdevices.cc
+++ b/techlibs/analogdevices/synth_analogdevices.cc
@@ -271,7 +271,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
 	void script() override
 	{
 		if (check_label("begin")) {
-			run(stringf("read_verilog -lib -specify %s +/analogdevices/cells_sim.v", tech_param));
+			run(stringf("read_techlib -lib -specify %s +/analogdevices/cells_sim.v", tech_param));
 			run(stringf("hierarchy -check %s", top_opt.c_str()));
 		}
 
@@ -456,7 +456,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
 			if (help_mode)
 				run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
 			else if (abc9) {
-				run("read_verilog -icells -lib -specify +/analogdevices/abc9_model.v");
+				run("read_techlib -icells -lib -specify +/analogdevices/abc9_model.v");
 				std::string abc9_opts;
 				std::string k = "synth_analogdevices.abc9.W";
 				if (active_design && active_design->scratchpad.count(k))
diff --git a/techlibs/anlogic/CMakeLists.txt b/techlibs/anlogic/CMakeLists.txt
index c3f967df1..40dfdd262 100644
--- a/techlibs/anlogic/CMakeLists.txt
+++ b/techlibs/anlogic/CMakeLists.txt
@@ -23,7 +23,7 @@ yosys_pass(synth_anlogic
 		opt
 		opt_expr
 		proc
-		read_verilog
+		read_techlib
 		simplemap
 		stat
 		synth
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 5c7c0b532..31acc5483 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -149,7 +149,7 @@ struct SynthAnlogicPass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
+			run("read_techlib -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/coolrunner2/CMakeLists.txt b/techlibs/coolrunner2/CMakeLists.txt
index a19290d92..a0fa42628 100644
--- a/techlibs/coolrunner2/CMakeLists.txt
+++ b/techlibs/coolrunner2/CMakeLists.txt
@@ -24,7 +24,7 @@ yosys_pass(synth_coolrunner2
 		iopadmap
 		opt
 		proc
-		read_verilog
+		read_techlib
 		splitnets
 		stat
 		synth
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index 1b30f51bc..30d1cec84 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -125,7 +125,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/coolrunner2/cells_sim.v");
+			run("read_techlib -lib +/coolrunner2/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/efinix/CMakeLists.txt b/techlibs/efinix/CMakeLists.txt
index 05dfc7885..6916aa9dc 100644
--- a/techlibs/efinix/CMakeLists.txt
+++ b/techlibs/efinix/CMakeLists.txt
@@ -20,7 +20,7 @@ yosys_pass(synth_efinix
 		opt
 		opt_expr
 		proc
-		read_verilog
+		read_techlib
 		simplemap
 		stat
 		synth
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index 14457c64b..054e187e6 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -141,7 +141,7 @@ struct SynthEfinixPass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/efinix/cells_sim.v");
+			run("read_techlib -lib +/efinix/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/fabulous/CMakeLists.txt b/techlibs/fabulous/CMakeLists.txt
index 53091e5d3..809127f76 100644
--- a/techlibs/fabulous/CMakeLists.txt
+++ b/techlibs/fabulous/CMakeLists.txt
@@ -19,7 +19,7 @@ yosys_pass(synth_fabulous
 		opt_expr
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		share
 		stat
 		techmap
diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc
index 0074a52af..00b3c4bd3 100644
--- a/techlibs/fabulous/synth_fabulous.cc
+++ b/techlibs/fabulous/synth_fabulous.cc
@@ -261,14 +261,14 @@ struct SynthPass : public ScriptPass
 	void script() override
 	{
 		if (plib.empty())
-			run(stringf("read_verilog %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : ""));
+			run(stringf("read_techlib %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : ""));
 		else
-			run("read_verilog -lib " + plib);
+			run("read_techlib -lib " + plib);
 
 		if (help_mode) {
-			run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)");
+			run("read_techlib -lib <extra_plib.v>", "(for each -extra-plib)");
 		} else for (auto lib : extra_plib) {
-			run("read_verilog -lib " + lib);
+			run("read_techlib -lib " + lib);
 		}
 
 		if (check_label("begin")) {
diff --git a/techlibs/gatemate/CMakeLists.txt b/techlibs/gatemate/CMakeLists.txt
index dbd8d745e..e6e2cf07b 100644
--- a/techlibs/gatemate/CMakeLists.txt
+++ b/techlibs/gatemate/CMakeLists.txt
@@ -36,7 +36,7 @@ yosys_pass(synth_gatemate
 		opt_expr
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		share
 		simplemap
 		stat
diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc
index 6861b6780..beb042088 100644
--- a/techlibs/gatemate/synth_gatemate.cc
+++ b/techlibs/gatemate/synth_gatemate.cc
@@ -219,7 +219,7 @@ struct SynthGateMatePass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
+			run("read_techlib -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/gowin/CMakeLists.txt b/techlibs/gowin/CMakeLists.txt
index f74305818..2252381b2 100644
--- a/techlibs/gowin/CMakeLists.txt
+++ b/techlibs/gowin/CMakeLists.txt
@@ -24,7 +24,7 @@ yosys_pass(synth_gowin
 		opt_lut_ins
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		setundef
 		share
 		simplemap
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index d5ebdafea..b125ff6db 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -257,8 +257,8 @@ struct SynthGowinPass : public ScriptPass
 
 		if (check_label("begin"))
 		{
-			run("read_verilog -specify -lib +/gowin/cells_sim.v");
-			run(stringf("read_verilog -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family));
+			run("read_techlib -specify -lib +/gowin/cells_sim.v");
+			run(stringf("read_techlib -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "<family>" : family));
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
@@ -362,12 +362,12 @@ struct SynthGowinPass : public ScriptPass
 		{
 			run("sort");
 			if (nowidelut && abc9) {
-				run("read_verilog -icells -lib -specify +/abc9_model.v");
+				run("read_techlib -icells -lib -specify +/abc9_model.v");
 				run("abc9 -maxlut 4 -W 500");
 			} else if (nowidelut && !abc9) {
 				run("abc -lut 4");
 			} else if (!nowidelut && abc9) {
-				run("read_verilog -icells -lib -specify +/abc9_model.v");
+				run("read_techlib -icells -lib -specify +/abc9_model.v");
 				run("abc9 -maxlut 8 -W 500");
 			} else if (!nowidelut && !abc9) {
 				run("abc -lut 4:8");
diff --git a/techlibs/greenpak4/CMakeLists.txt b/techlibs/greenpak4/CMakeLists.txt
index c721bdc0d..0358c5d84 100644
--- a/techlibs/greenpak4/CMakeLists.txt
+++ b/techlibs/greenpak4/CMakeLists.txt
@@ -21,7 +21,7 @@ yosys_pass(synth_greenpak4
 		nlutmap
 		opt
 		proc
-		read_verilog
+		read_techlib
 		shregmap
 		stat
 		synth
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 7f91d6332..675f89ab2 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -137,7 +137,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/greenpak4/cells_sim.v");
+			run("read_techlib -lib +/greenpak4/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/ice40/CMakeLists.txt b/techlibs/ice40/CMakeLists.txt
index f925e6956..b9ff13618 100644
--- a/techlibs/ice40/CMakeLists.txt
+++ b/techlibs/ice40/CMakeLists.txt
@@ -55,7 +55,7 @@ yosys_pass(synth_ice40
 		opt_lut
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		select
 		setattr
 		share
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 86189c848..b98f9ebc3 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -301,7 +301,7 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (check_label("begin"))
 		{
-			run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
+			run("read_techlib " + define + " -lib -specify +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 			run("proc");
 		}
@@ -416,7 +416,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc9) {
-					run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
+					run("read_techlib " + define + " -icells -lib -specify +/ice40/abc9_model.v");
 					std::string abc9_opts;
 					std::string k = "synth_ice40.abc9.W";
 					if (active_design && active_design->scratchpad.count(k))
diff --git a/techlibs/intel/CMakeLists.txt b/techlibs/intel/CMakeLists.txt
index a0b321edb..9bcca1f01 100644
--- a/techlibs/intel/CMakeLists.txt
+++ b/techlibs/intel/CMakeLists.txt
@@ -21,7 +21,7 @@ yosys_pass(synth_intel
 		opt_expr
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		setundef
 		stat
 		techmap
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 0b0eb6ae9..88618f4a3 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -188,11 +188,11 @@ struct SynthIntelPass : public ScriptPass {
 	{
 		if (check_label("begin")) {
 			if (check_label("family"))
-				run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt));
+				run(stringf("read_techlib -sv -lib +/intel/%s/cells_sim.v", family_opt));
 
 			// Misc and common cells
-			run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
-			run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
+			run("read_techlib -sv -lib +/intel/common/m9k_bb.v");
+			run("read_techlib -sv -lib +/intel/common/altpll_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/intel_alm/CMakeLists.txt b/techlibs/intel_alm/CMakeLists.txt
index fa8c7fd46..1750719ca 100644
--- a/techlibs/intel_alm/CMakeLists.txt
+++ b/techlibs/intel_alm/CMakeLists.txt
@@ -22,7 +22,7 @@ yosys_pass(synth_intel_alm
 		opt_expr
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		share
 		stat
 		techmap
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 95dbb6e35..fd02f39ac 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -169,16 +169,16 @@ struct SynthIntelALMPass : public ScriptPass {
 
 		if (check_label("begin")) {
 			if (family_opt == "cyclonev")
-				run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt));
-			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt));
-			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt));
-			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt));
-			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt));
-			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt));
-			run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt));
+				run(stringf("read_techlib -sv -lib +/intel_alm/%s/cells_sim.v", family_opt));
+			run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt));
+			run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt));
+			run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt));
+			run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt));
+			run(stringf("read_techlib -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt));
+			run(stringf("read_techlib -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt));
 			// Misc and common cells
-			run("read_verilog -lib +/intel/common/altpll_bb.v");
-			run("read_verilog -lib +/intel_alm/common/megafunction_bb.v");
+			run("read_techlib -lib +/intel/common/altpll_bb.v");
+			run("read_techlib -lib +/intel_alm/common/megafunction_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/lattice/CMakeLists.txt b/techlibs/lattice/CMakeLists.txt
index 8f0557c27..d978c5f5d 100644
--- a/techlibs/lattice/CMakeLists.txt
+++ b/techlibs/lattice/CMakeLists.txt
@@ -40,7 +40,7 @@ yosys_pass(synth_lattice
 		opt_merge
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		share
 		simplemap
 		stat
diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc
index 43fb7b1c2..4f6cd9006 100644
--- a/techlibs/lattice/synth_lattice.cc
+++ b/techlibs/lattice/synth_lattice.cc
@@ -395,7 +395,7 @@ struct SynthLatticePass : public ScriptPass
 
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v");
+			run("read_techlib -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/microchip/CMakeLists.txt b/techlibs/microchip/CMakeLists.txt
index 491315f77..e8f2d226e 100644
--- a/techlibs/microchip/CMakeLists.txt
+++ b/techlibs/microchip/CMakeLists.txt
@@ -47,7 +47,7 @@ yosys_pass(synth_microchip
 		opt_expr
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		select
 		setattr
 		share
diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc
index 218ed310f..9802abc84 100644
--- a/techlibs/microchip/synth_microchip.cc
+++ b/techlibs/microchip/synth_microchip.cc
@@ -260,7 +260,7 @@ struct SynthMicrochipPass : public ScriptPass {
 		if (check_label("begin")) {
 			std::string read_args;
 			read_args += " -lib -specify +/microchip/cells_sim.v";
-			run("read_verilog" + read_args);
+			run("read_techlib" + read_args);
 
 			run(stringf("hierarchy -check %s", top_opt));
 		}
diff --git a/techlibs/nanoxplore/CMakeLists.txt b/techlibs/nanoxplore/CMakeLists.txt
index db5479ed6..7cc5f1201 100644
--- a/techlibs/nanoxplore/CMakeLists.txt
+++ b/techlibs/nanoxplore/CMakeLists.txt
@@ -27,7 +27,7 @@ yosys_pass(synth_nanoxplore
 		opt_merge
 		peepopt
 		proc
-		read_verilog
+		read_techlib
 		setundef
 		share
 		stat
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index 0b87c98c7..ddf4a6b13 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -241,7 +241,7 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
+			run("read_techlib -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
 			run("techmap -map +/nanoxplore/cells_wrap.v");
 			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
diff --git a/techlibs/quicklogic/CMakeLists.txt b/techlibs/quicklogic/CMakeLists.txt
index 8d7409056..9e03830ac 100644
--- a/techlibs/quicklogic/CMakeLists.txt
+++ b/techlibs/quicklogic/CMakeLists.txt
@@ -63,7 +63,7 @@ yosys_pass(synth_quicklogic
 		ql_dsp_macc
 		ql_dsp_simd
 		ql_ioff
-		read_verilog
+		read_techlib
 		setundef
 		share
 		shregmap
diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc
index e65be1c58..16a76eade 100644
--- a/techlibs/quicklogic/synth_quicklogic.cc
+++ b/techlibs/quicklogic/synth_quicklogic.cc
@@ -198,7 +198,7 @@ struct SynthQuickLogicPass : public ScriptPass {
 		}
 
 		if (check_label("begin")) {
-			std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path, lib_path, family);
+			std::string read_simlibs = stringf("read_techlib -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path, lib_path, family);
 			if (family == "qlf_k6n10f") {
 				read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path);
 				if (bramTypes)
@@ -317,7 +317,7 @@ struct SynthQuickLogicPass : public ScriptPass {
 		if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
 			run("techmap -map " + lib_path + family + "/latches_map.v");
 			if (abc9) {
-				run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");
+				run("read_techlib -lib -specify -icells " + lib_path + family + "/abc9_model.v");
 				run("techmap -map " + lib_path + family + "/abc9_map.v");
 				run("abc9 -maxlut 4 -dff");
 				run("techmap -map " + lib_path + family + "/abc9_unmap.v");
diff --git a/techlibs/sf2/CMakeLists.txt b/techlibs/sf2/CMakeLists.txt
index 19b67daa5..9a8bc26e6 100644
--- a/techlibs/sf2/CMakeLists.txt
+++ b/techlibs/sf2/CMakeLists.txt
@@ -16,7 +16,7 @@ yosys_pass(synth_sf2
 		opt
 		opt_expr
 		proc
-		read_verilog
+		read_techlib
 		simplemap
 		stat
 		synth
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 7a7f87466..16aca4a83 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -165,7 +165,7 @@ struct SynthSf2Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/sf2/cells_sim.v");
+			run("read_techlib -lib +/sf2/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
 		}
 
diff --git a/techlibs/xilinx/CMakeLists.txt b/techlibs/xilinx/CMakeLists.txt
index ccc432552..328181c3b 100644
--- a/techlibs/xilinx/CMakeLists.txt
+++ b/techlibs/xilinx/CMakeLists.txt
@@ -58,7 +58,7 @@ yosys_pass(synth_xilinx
 		peepopt
 		pmux2shiftx
 		proc
-		read_verilog
+		read_techlib
 		select
 		setattr
 		share
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b08fbe499..c475af854 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -346,9 +346,9 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("begin")) {
 			std::string read_args;
 			read_args += " -lib -specify +/xilinx/cells_sim.v";
-			run("read_verilog" + read_args);
+			run("read_techlib" + read_args);
 
-			run("read_verilog -lib +/xilinx/cells_xtra.v");
+			run("read_techlib -lib +/xilinx/cells_xtra.v");
 
 			run(stringf("hierarchy -check %s", top_opt));
 		}
@@ -651,7 +651,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
 							"will use timing for 'xc7' instead.\n", family.c_str());
-				run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
+				run("read_techlib -icells -lib -specify +/xilinx/abc9_model.v");
 				std::string abc9_opts;
 				std::string k = "synth_xilinx.abc9.W";
 				if (active_design && active_design->scratchpad.count(k))