mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #6068 from YosysHQ/emil/aigmap-remove-unused-cache
aigmap: remove unused and_cache
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commit
07a615a283
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@ -92,7 +92,6 @@ struct AigmapPass : public Pass {
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}
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}
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vector<SigBit> sigs;
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vector<SigBit> sigs;
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dict<pair<int, int>, SigBit> and_cache;
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for (int node_idx = 0; node_idx < GetSize(aig.nodes); node_idx++)
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for (int node_idx = 0; node_idx < GetSize(aig.nodes); node_idx++)
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{
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{
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@ -115,15 +114,10 @@ struct AigmapPass : public Pass {
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goto skip_inverter;
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goto skip_inverter;
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} else {
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} else {
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pair<int, int> key(node.left_parent, node.right_parent);
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bit = module->addWire(NEW_ID);
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if (and_cache.count(key))
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auto gate = module->addAndGate(NEW_ID, A, B, bit);
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bit = and_cache.at(key);
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if (select_mode)
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else {
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new_sel.insert(gate->name);
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bit = module->addWire(NEW_ID);
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auto gate = module->addAndGate(NEW_ID, A, B, bit);
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if (select_mode)
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new_sel.insert(gate->name);
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}
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}
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}
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}
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}
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