mirror of
https://github.com/YosysHQ/yosys.git
synced 2026-10-06 01:53:53 +02:00
SigMap performance improvement
This commit is contained in:
+7
-1
@@ -242,7 +242,13 @@ struct SigMap
|
||||
|
||||
void set(RTLIL::Module *module)
|
||||
{
|
||||
clear();
|
||||
int bitcount = 0;
|
||||
for (auto &it : module->connections())
|
||||
bitcount += it.first.size();
|
||||
|
||||
database.clear();
|
||||
database.reserve(bitcount);
|
||||
|
||||
for (auto &it : module->connections())
|
||||
add(it.first, it.second);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user