mirror of https://github.com/YosysHQ/yosys.git
20 lines
395 B
Plaintext
20 lines
395 B
Plaintext
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log -header "Simple positive case (same width)"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, b, y);
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input wire signed [7:0] a;
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input wire signed [7:0] b;
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output wire signed [7:0] y;
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assign y = (-a) + (-b);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -post
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 1 t:$neg
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design -reset
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log -pop
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