mirror of https://github.com/YosysHQ/yosys.git
14 lines
205 B
Plaintext
14 lines
205 B
Plaintext
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read_verilog <<EOT
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module top(input a, b, output c);
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bb #(1) bb();
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endmodule
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module bb(input a, b, output c);
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parameter p = 0;
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assign c = a ^ b;
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endmodule
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EOT
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blackbox bb
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hierarchy
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write_xaiger /dev/null
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