yosys/tests/liberty/XNOR2X1.lib.verilogsim.ok

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module XNOR2X1 (B, A, Y);
  input B;
  input A;
  output Y;
  assign Y = !(B&!A|!B&A); // "!(B&!A|!B&A)"
endmodule
Extend liberty tests 2024-08-13 18:36:31 +02:00			`module XNOR2X1 (B, A, Y);`
			`input B;`
			`input A;`
			`output Y;`
Fix existing tests/liberty tests, and add them to Makefile. 2025-04-03 18:56:24 +02:00			`assign Y = !(B&!A\|!B&A); // "!(B&!A\|!B&A)"`
Extend liberty tests 2024-08-13 18:36:31 +02:00			`endmodule`