Xschem is targeted for VLSI design, and as such it is built around the concept of vector nets, vector ports and vector instances.
A simple example of a vectored instance wired with vector nets is shown below:
This simple placement is equivalent to placing 32 single xrdec[31], xrdec[30], ..., xrdec[0] blocks.
If you look at the LDWL[511:0] net it represents a bus of 512 wires. Wires LDWL[511:496] will be connected to instance xrdec[31], wires LDWL[495:480] will be connected to xrdec[30] and so on.
See this design where 16 blocks are all wired manually to wide buses:
The same design can be expressed in this compact form.
This compact form is way easier to draw and less prone to typos.
just as a note the notation x[60:0:4] means a bundle of the following bits: x[60], x[56], x[52], ..., x[0].
The leftmost instance (x1[15] in the example below) connects to the leftmost bits of the bus, that is:
x115
----------------------
| |
x[60] --| x[0] |
| |
----------------------
For more info on bus / vector notation see the manual page.