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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
287 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
Other 1.7%
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Stefan Frederik fdfe32d8ef updated Changelog 2020-11-20 19:26:13 +01:00
XSchemWin updated Changelog 2020-11-20 19:26:13 +01:00
doc "Delete files" menu command added 2020-10-24 23:46:19 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src allow to pass down to tcl evaluation (via tcleval( ....) wrap) instance parameters: example of a mos transistor : name=m1 w=2 l=0.13 model=net ad="tcleval([expr @W * 0.29])" --> in netlist: m1 d g s b nfet w=2 l=0.13 ... ad=0.58 2020-11-20 18:46:27 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library reduce svg size by avoiding redundant attributes in elements, fix a regression in scheduler.c (missing else clause) 2020-11-18 23:20:50 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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Changelog updated Changelog 2020-11-20 19:26:13 +01:00
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LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
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config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions