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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
894 Commits 3 Branches 10 Tags 86 MiB
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Stefan Frederik fdf93666b4 fix the hardest bug ever in master graph x-axis zooming (f**k!) 2022-01-06 07:37:44 +01:00
XSchemWin fix BadDrawable regression in free_rawfile(): after deleting data a draw() was called, but since this function is called also in exit handler all windows are already closed. Added digital waveforms and bussed signal display 2021-12-29 05:11:39 +01:00
doc doc updates about menu text change 2021-12-01 15:03:10 +01:00
scconfig updated xschemtest.tcl with new hashes 2021-12-22 11:11:46 +01:00
src fix the hardest bug ever in master graph x-axis zooming (f**k!) 2022-01-06 07:37:44 +01:00
tests speed optimizations in draw_graph() 2022-01-01 21:47:17 +01:00
xschem_library various regressions due to refactoring fixed 2022-01-06 01:10:06 +01:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions