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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,274 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
Other 1.7%
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Stefan Frederik fd72e72dba test and got svg_embedded_graph(...) to work on Windows with Cairo (Joanne). added some #ifndef __unix__ guards to avoid compiler warnings about defined and not used functions, initial implementation of "Recent components" browser. 2022-09-25 21:11:52 +02:00
XSchemWin xschem raw_read accepts an optional type argument after file name (tran, ac, dc, op, ...) to select type of simulation to load from raw file. New command xschem annotate_op will replace ngspice::annotate tcl procedure. 2022-09-20 16:49:42 +02:00
doc updated docs with additional video on graphs and Xyce sim 2022-09-22 13:45:55 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src test and got svg_embedded_graph(...) to work on Windows with Cairo (Joanne). added some #ifndef __unix__ guards to avoid compiler warnings about defined and not used functions, initial implementation of "Recent components" browser. 2022-09-25 21:11:52 +02:00
tests bypass tcl for voltage and current backannotation in schematic from cursor b positon in graph 2022-09-20 03:12:46 +02:00
xschem_library update solar_panel.sch 2022-09-23 02:47:55 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions