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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers fc19e646c7 set default live_cursor2_backannotate to 1 (enabled) 2024-03-26 15:39:16 +01:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin cleanups in draw_image(), do not decode-reencode jpeg data 2024-03-16 12:50:42 +01:00
doc cairo_font_scale can be changed runtime to rescale text fonts, hier_hilight_hash_lookup(() function to hilight an arbitrary hierarchic net; improved xschem list_hilights command 2024-03-24 19:34:30 +01:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src set default live_cursor2_backannotate to 1 (enabled) 2024-03-26 15:39:16 +01:00
tests hash_file(): skip also .include lines if skip_path_lines parameter is set 2024-03-20 10:45:28 +01:00
xschem_library fourth round of additions to improve auto_hilight_graph_nodes 2024-03-26 01:21:37 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions