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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers fa4d4a0970 enhance spice_sym_def used in instances (with schematic=...) by substituting @param with values defined in instance if any (param=xxx) 2024-06-14 08:55:35 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin proc ev, ev0, to_eng: evaluate expr at global scope so global vars will be expanded correctly ($path) 2024-05-29 09:41:52 +02:00
doc doc updates (dataset specification in graphs.html) 2024-06-11 15:14:41 +02:00
scconfig allow @symname , @param (param defined in symbol template string) translation in instance or symbol spice_sym_def attributes 2024-06-14 08:21:43 +02:00
src enhance spice_sym_def used in instances (with schematic=...) by substituting @param with values defined in instance if any (param=xxx) 2024-06-14 08:55:35 +02:00
tests tests/netlisting.tcl: better error checking. Distinguish a general failure from an ERC netlist error (xschem return code 10) 2024-05-17 00:48:47 +02:00
xschem_library fix bus_tap netlisting with bus pin (pin # 1) connected to unnamed net. If Tap pin (pin # 0) was already named as #net... (unnamed net ) delete and take name from bus pin and tap index 2024-05-31 11:50:02 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog to 3.4.5 2024-05-28 16:46:26 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions