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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers f847b61333 Gerard upates for Xschem <--> BeSpice TCP communication 2023-07-25 23:33:46 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin avoid using "string is list" if tclversion <= 8.4 2023-06-28 00:32:56 +02:00
doc update docs about parametrized subcircuits, add braces around parameters (some ngspice version require them, some other can live without for simple non expression params), Update text example comp_ngspice.sch 2023-07-13 21:13:56 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src Gerard upates for Xschem <--> BeSpice TCP communication 2023-07-25 23:33:46 +02:00
tests add xschemrc variable "ps_paper_size" to specify custom paper sizes in ps/pdf exports 2023-07-12 08:10:00 +02:00
xschem_library update docs about parametrized subcircuits, add braces around parameters (some ngspice version require them, some other can live without for simple non expression params), Update text example comp_ngspice.sch 2023-07-13 21:13:56 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog bump to version 3.4.1, updated Changelog 2023-06-29 21:40:49 +02:00
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LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions