A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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Stefan Schippers f419381361 added support for probing waveforms into gaw if raw file written by Xyce; Xyce uses uppercase, does not wrap voltage nodes into V(...). uses ":" instead of "." as hierarchy separator and other quirks.		2020-10-09 01:21:27 +02:00
XSchemWin	various graphic rendering fixes for the new "view instance pin net names" function. Fixed some errors in merge schematic in callback.c and paste.c	2020-10-02 03:21:22 +02:00
doc	doc updates	2020-09-30 01:34:18 +02:00
scconfig	"xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg)	2020-09-22 13:35:55 +02:00
src	added support for probing waveforms into gaw if raw file written by Xyce; Xyce uses uppercase, does not wrap voltage nodes into V(...). uses ":" instead of "." as hierarchy separator and other quirks.	2020-10-09 01:21:27 +02:00
tests	better wire connecting bubble zoom scaling at different snap levels	2020-10-07 19:45:40 +02:00
xschem_library	some clarifications of steps to be taken to simulate example rom8k circuit	2020-10-08 23:24:27 +02:00
.gitignore	changed .gitignore for specific xschem files	2020-08-08 23:25:43 +02:00
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Changelog	fix Browse button in edit symbol prop dialog	2020-09-15 14:15:43 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions