A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Go to file

Stefan Frederik ecca24191e fixes in fullscreen code (restore zoom lavels)		2022-09-04 14:16:38 +02:00
XSchemWin	add xschem get zoom to query zoom factor	2022-08-24 11:22:26 +02:00
doc	sys-lib-path: add /devices in configure log shown text	2022-08-13 11:02:18 +02:00
scconfig	monospaced font in code_shown.sym	2022-08-30 15:54:18 +02:00
src	fixes in fullscreen code (restore zoom lavels)	2022-09-04 14:16:38 +02:00
tests	remove extra blank in .subckt spice netlist lines	2022-08-18 12:14:23 +02:00
xschem_library	monospaced font in code_shown.sym	2022-08-30 15:54:18 +02:00
.gitignore	changed .gitignore for specific xschem files	2020-08-08 23:25:43 +02:00
AUTHORS	update copyright info to 2021; update Product.wxs	2021-09-12 08:32:16 +02:00
Changelog	Update Changelog	2022-07-28 10:31:07 +02:00
INSTALL	populating xschem git repo	2020-08-08 15:47:34 +02:00
LICENSE	update license info	2021-07-27 16:42:54 +02:00
Makefile	populating xschem git repo	2020-08-08 15:47:34 +02:00
Makefile.conf.in	populating xschem git repo	2020-08-08 15:47:34 +02:00
README	update license info	2021-07-27 16:42:54 +02:00
README.md	Update README.md	2020-10-08 00:54:06 +02:00
README_MacOS.md	added notes for MacOS 'Big Sur' builds.	2021-09-26 13:24:51 +02:00
config.h.in	remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables	2022-01-19 00:49:46 +01:00
configure	populating xschem git repo	2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions