A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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Chayan Deb ec8ba527e3 Merge pull request #3 from TheSUPERCD/upstream-clone Resolved merge conflicts and integrated upstream changes into this fork. Future merge conflicts will be resolved this way (using local upstream-clone to resolve merge-conflicts).		2025-01-25 12:17:30 +05:30
.github/workflows	Configure github CI	2023-05-06 02:04:30 +02:00
XSchemWin	str_replace(): add parameter to specify number of substituitions (or all); replaced atof_spice() with atof_eng() in various parts related to numbers that do not come from spice netlists; fix numerical setting of cursors if log scale is set (wrong preset was shown); make wave labels in graph scale with gr->magx as X-axis labels; fix scaling roundoff issues in dtoa_eng(); add new `@spice_get_node <spice_node> ` token (where spice_node may contain @variables) in symbol texts to display indicated spice node value. Does not use TCL, thus faster and less "quoting hell" problems	2025-01-10 01:52:54 +01:00
doc	add `xschem draw_hilight_net [on_window]` for quick draw or hilighted objects; add `xschem get_sim_sch` to get the current schematic hierarchy path, stripping off levels above the level the raw file was loaded. Strip off also leading dot; `xschem hilight_instname`: move fast option as -fast option; list_nets(): expand vector ports ; optimize update_op() for speed	2025-01-24 18:57:35 +01:00
scconfig	fix some c89 violations (warnings)	2025-01-10 16:14:24 +01:00
src	Merge branch 'master' into upstream-clone	2025-01-25 12:15:55 +05:30
tests	allow `xschem translate -1 string` to translate tokens that do not depend on specific instances; yet another change in wrap detection in graphs, always use simulator sweep-var instead of user specified sweep variable; simulated data will never wrap exactly to first value due to roundoff errors; -fast optionto `xschem hilight_netname` command	2025-01-24 03:52:20 +01:00
xschem_library	allow `xschem translate -1 string` to translate tokens that do not depend on specific instances; yet another change in wrap detection in graphs, always use simulator sweep-var instead of user specified sweep variable; simulated data will never wrap exactly to first value due to roundoff errors; -fast optionto `xschem hilight_netname` command	2025-01-24 03:52:20 +01:00
.gitignore	gitignore update	2023-01-16 13:41:16 -07:00
AUTHORS	update copyright info to 2021; update Product.wxs	2021-09-12 08:32:16 +02:00
CMakeLists.txt	Added png and embedded graphs to ps and pdf export	2023-01-15 21:34:43 -07:00
Changelog	update Changelog	2024-12-16 17:01:38 +01:00
INSTALL	populating xschem git repo	2020-08-08 15:47:34 +02:00
LICENSE	update license info	2021-07-27 16:42:54 +02:00
Makefile	make uninstall: remove empty directories (share/xschem and share/doc/xschem); make command `xschem help` work also if running in src/ directory; use XSCHEM_SHAREDIR shell variable (if defined and directory existing), else set XCSCHEM_SHAREDIR to `pwd` if started from src/ dir, else set compile set XSCHEM_SHAREDIR. xschemrc can override this XSCHEM_SHAREDIR setting.	2025-01-05 01:29:04 +01:00
Makefile.conf.in	remove check for libreadline (not used)	2024-11-13 01:35:24 +01:00
README	update license info	2021-07-27 16:42:54 +02:00
README.md	Update README.md	2020-10-08 00:54:06 +02:00
README_MacOS.md	added notes for MacOS 'Big Sur' builds.	2021-09-26 13:24:51 +02:00
config.h.in	remove check for libreadline (not used)	2024-11-13 01:35:24 +01:00
configure	populating xschem git repo	2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions