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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
2,070 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
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Stefan Schippers e7c53b59b5 callback(): filter out any state value that uses bits above 12 2023-09-27 18:35:40 +02:00
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XSchemWin fix garbage on screen if drawing something, go to another tab, return and move objects. Regression was introduced on repo.hu r3033 2023-09-27 13:13:15 +02:00
doc FIX_BROKEN_TILED_FILL can now be changed runtime (fix_broken_tiled_fill) 2023-09-27 01:28:31 +02:00
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xschem_library revert a change in example schematic pcb_test1.sch so xschemtest will not report a false error 2023-09-20 12:35:26 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions