luke
/
xschem
mirror of https://github.com/StefanSchippers/xschem.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
121 Commits 3 Branches 10 Tags 87 MiB
C 71.5%
Tcl 15.7%
Awk 8.2%
Roff 2%
Yacc 0.7%
Other 1.8%
Go to file
Stefan Schippers e7b0a5b9a3 better read_line(): handle unextected EOFs (noeol last lines) 2020-09-28 15:21:26 +02:00
XSchemWin Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
doc add attributes "weight=bold", "slant=italic", "slant=oblique" on text objects for bold/italic/oblique texts, doc updates. 2020-09-23 18:15:26 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src better read_line(): handle unextected EOFs (noeol last lines) 2020-09-28 15:21:26 +02:00
tests Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
xschem_library completely eliminated match_symbol() (which in turn may call load_sym_def() ) calls from within load_sym_def(), even for aligning LCC schematic pin ordering to symbol. A dedicated "align_sch_pins_with_sym()" together with "get_sym_type()" does the job in O(N) instead of using a sort routine. 2020-09-27 12:41:36 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS populating xschem git repo 2020-08-08 15:47:34 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog fix Browse button in edit symbol prop dialog 2020-09-15 14:15:43 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE added LICENSE 2020-08-09 09:12:07 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Add manual link 2020-08-08 16:04:20 +02:00
config.h.in populating xschem git repo 2020-08-08 15:47:34 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse. Manual and instructions: http://repo.hu/projects/xschem/xschem_man/xschem_man.html