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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
2,117 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
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stefan schippers e457292e04 trim_chars() function for various string operations 2023-10-11 16:31:42 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin further fix expandlabel() potentially returning its string argument (instead of a copy) in case of weird and wrong node syntax 2023-10-06 11:11:17 +02:00
doc first selected instance is now always the master (instead of the first in the xschem array order) when doing an edit attribute on a group of selected elements 2023-10-04 17:15:52 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src trim_chars() function for various string operations 2023-10-11 16:31:42 +02:00
tests more robust netlist_test proc in xschemtest.tcl 2023-08-28 11:44:12 +02:00
xschem_library do not duplicate empty strings as NULLs in hash tables 2023-10-09 12:49:11 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions