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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
808 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
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Stefan Frederik e2db38c881 statement reordering for faster execution in my_round() 2021-12-17 23:56:25 +01:00
XSchemWin do not hash the comments containing absolute paths in xschemtest netlist check, since these vary on different systems 2021-12-14 12:40:32 +01:00
doc doc updates about menu text change 2021-12-01 15:03:10 +01:00
scconfig old_winpath[] removed from globals, put as static string into callback(), fix ngspice::annotate netlist_dir fetching. 2021-11-23 23:20:10 +01:00
src statement reordering for faster execution in my_round() 2021-12-17 23:56:25 +01:00
tests preserve line ordering regardless of awk hash implementation in tedax netlists as done for vhdl and verilog; include a couple of tedax netlist checks in xschemtest 2021-12-16 00:39:09 +01:00
xschem_library rename xschem_simulator/ n.sym and p.sym to ntrans.sym and ptrans.sym to avoid confusion with symbols in rom8k/; place tk_messageBox above right xschem window when using multiple (single process) windows. 2021-12-17 03:29:53 +01:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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Changelog bump version to 3.0.0; prepare for 3.0.0 release 2021-09-11 07:53:11 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions