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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik db8186c213 fix mapping issue in hiertEDAx code. Thanks to Hannu for pointing it out. Allow newlines in (quoted) long vector labels, like: "AAA,BBB,\nCCC,DDD,EEE" 2020-11-30 21:01:33 +01:00
XSchemWin added some comments 2020-11-26 04:01:11 +01:00
doc removed event_reporting feature 2020-11-29 03:27:45 +01:00
scconfig added some comments 2020-11-26 04:01:11 +01:00
src fix mapping issue in hiertEDAx code. Thanks to Hannu for pointing it out. Allow newlines in (quoted) long vector labels, like: "AAA,BBB,\nCCC,DDD,EEE" 2020-11-30 21:01:33 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library more consistent get_tok_value() regarding escaping 2020-11-29 01:59:17 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions