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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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tests get_additional_symbols(): some sanity checks, descend_schematic() more options in set_title argument (avoid set title, avoid processing pins/nets, avoid descending into i-th xdec[3] instance, descend as a whole xdec[3:0], add `xschem get_additional_symbols what` command, allow `xschem get_sch_from_sym -1 inv.sym` to get schematic associated with symbol. hier_psprint(): avoid printing / listing duplicate schematics, improved traversal.tcl 2024-11-05 13:59:37 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions