A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Go to file
stefan schippers d529f21d88 do not start xctx->drag_elements if xctx->poly_point_selected is set 2024-03-03 05:15:51 +01:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin recognize integrated_noise, improve `xschem preview_window` command 2024-01-27 11:42:05 +01:00
doc minor doc updates 2024-03-02 12:03:40 +01:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src do not start xctx->drag_elements if xctx->poly_point_selected is set 2024-03-03 05:15:51 +01:00
tests update hash for greycnt.sch in xschemtest.tcl 2024-01-04 00:09:28 +01:00
xschem_library update docs for polygon editing (point drag, add/delete points), xschem logo update 2024-03-02 11:48:52 +01:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog for 3.4.4 2023-10-05 08:06:47 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in Add description for FIX_BROKEN_TILED_FILL in config.h.in 2023-09-22 01:21:32 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions