55 lines
1.8 KiB
Plaintext
55 lines
1.8 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=stdcell
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xfunction3="0 d ~ 3 & x 1 & | 2 &"
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function3="3 1 0 M L 2 ~ M"
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format="@name @@CLK @@D @@RESET_B @VGND @VNB @VPB @VPWR @@Q @prefix\\\\dfrtp_1"
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template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ "
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extra="VGND VNB VPB VPWR prefix"
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highlight=true
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}
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V {}
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S {}
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E {}
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L 4 -70 -30 70 -30 {}
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L 4 -70 30 70 30 {}
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L 4 -70 -30 -70 30 {}
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L 4 70 -30 70 30 {}
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L 4 -90 -20 -70 -20 {}
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L 4 -90 0 -70 0 {}
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L 4 -90 20 -70 20 {}
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L 4 70 -20 90 -20 {}
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B 5 -92.5 -22.5 -87.5 -17.5 {name=CLK dir=in
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goto=3 clock=1}
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B 5 -92.5 -2.5 -87.5 2.5 {name=D dir=in }
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B 5 -92.5 17.5 -87.5 22.5 {name=RESET_B dir=in
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goto=3
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clock=2}
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B 5 87.5 -22.5 92.5 -17.5 {name=Q dir=out }
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T {@symname} 0 -6 0 0 0.3 0.3 {hcenter=true}
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T {@name} 75 -42 0 0 0.2 0.2 {}
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T {CLK} -65 -24 0 0 0.2 0.2 {}
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T {D} -65 -4 0 0 0.2 0.2 {}
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T {RESET_B} -65 16 0 0 0.2 0.2 {}
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T {Q} 65 -24 0 1 0.2 0.2 {}
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