v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=stdcell
xfunction3="0 d ~ 3 & x 1 & | 2 &"
function3="3 1 0 M L 2 ~ M"
format="@name @@CLK @@D @@RESET_B @VGND @VNB @VPB @VPWR @@Q @prefix\\\\dfrtp_1"
template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ "
extra="VGND VNB VPB VPWR prefix"
highlight=true
}
V {}
S {}
E {}
L 4 -70 -30 70 -30 {}
L 4 -70 30 70 30 {}
L 4 -70 -30 -70 30 {}
L 4 70 -30 70 30 {}
L 4 -90 -20 -70 -20 {}
L 4 -90 0 -70 0 {}
L 4 -90 20 -70 20 {}
L 4 70 -20 90 -20 {}
B 5 -92.5 -22.5 -87.5 -17.5 {name=CLK dir=in 
goto=3 clock=1}
B 5 -92.5 -2.5 -87.5 2.5 {name=D dir=in }
B 5 -92.5 17.5 -87.5 22.5 {name=RESET_B dir=in 
goto=3
clock=2}
B 5 87.5 -22.5 92.5 -17.5 {name=Q dir=out }
T {@symname} 0 -6 0 0 0.3 0.3 {hcenter=true}
T {@name} 75 -42 0 0 0.2 0.2 {}
T {CLK} -65 -24 0 0 0.2 0.2 {}
T {D} -65 -4 0 0 0.2 0.2 {}
T {RESET_B} -65 16 0 0 0.2 0.2 {}
T {Q} 65 -24 0 1 0.2 0.2 {}