58 lines
1.8 KiB
Plaintext
58 lines
1.8 KiB
Plaintext
v {xschem version=3.4.6 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=opamp_va
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format="@name @@OUT @@IN1 @@IN2 @model"
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template="name=X1 model=diff_amp_cell"
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device_model="tcleval(
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.subckt diff_amp_cell OUT IN1 IN2
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N1 out in1 in2 diff_amp_model
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.ends diff_amp_cell
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.model diff_amp_model diff_amp
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.control
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* following line specifies the location for the .osdi file so ngspice can use it.
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pre_osdi $USER_CONF_DIR/xschem_library/diff_amp.osdi
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.endc
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)"
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}
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V {}
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S {}
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E {}
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L 4 -100 -40 -80 -40 {}
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L 4 80 0 100 0 {}
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L 4 -100 40 -80 40 {}
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B 5 97.5 -2.5 102.5 2.5 {name=OUT dir=out}
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B 5 -102.5 -42.5 -97.5 -37.5 {name=IN1 dir=in}
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B 5 -102.5 37.5 -97.5 42.5 {name=IN2 dir=in}
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P 4 4 -80 80 -80 -80 80 -0 -80 80 {}
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T {@symname} -64 -6 0 0 0.3 0.3 {}
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T {@name} 85 -22 0 0 0.2 0.2 {}
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T {IN1} -75 -44 0 0 0.2 0.2 {}
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T {OUT} 65 -4 0 1 0.2 0.2 {}
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T {IN2} -75 36 0 0 0.2 0.2 {}
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T {Ensure port order matches the
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order in the verilog-A file.} -30 -70 0 0 0.1 0.1 {hide=instance}
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