v {xschem version=3.4.6 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=opamp_va
format="@name @@OUT @@IN1 @@IN2 @model"

template="name=X1 model=diff_amp_cell"

device_model="tcleval(
.subckt diff_amp_cell OUT IN1 IN2
N1 out in1 in2 diff_amp_model
.ends diff_amp_cell

.model diff_amp_model diff_amp

.control
* following line specifies the location for the .osdi file so ngspice can use it.
pre_osdi $USER_CONF_DIR/xschem_library/diff_amp.osdi
.endc
)"
}
V {}
S {}
E {}
L 4 -100 -40 -80 -40 {}
L 4 80 0 100 0 {}
L 4 -100 40 -80 40 {}
B 5 97.5 -2.5 102.5 2.5 {name=OUT dir=out}
B 5 -102.5 -42.5 -97.5 -37.5 {name=IN1 dir=in}
B 5 -102.5 37.5 -97.5 42.5 {name=IN2 dir=in}
P 4 4 -80 80 -80 -80 80 -0 -80 80 {}
T {@symname} -64 -6 0 0 0.3 0.3 {}
T {@name} 85 -22 0 0 0.2 0.2 {}
T {IN1} -75 -44 0 0 0.2 0.2 {}
T {OUT} 65 -4 0 1 0.2 0.2 {}
T {IN2} -75 36 0 0 0.2 0.2 {}
T {Ensure port order matches the
order in the verilog-A file.} -30 -70 0 0 0.1 0.1 {hide=instance}