35 lines
1.3 KiB
Plaintext
35 lines
1.3 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=connector
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format="*connector(1,1) @pinlist"
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tedax_format="footprint @name @footprint"
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template="name=c1 footprint=connector(1,1)"}
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V {}
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S {}
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E {}
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B 5 -1.25 -1.25 1.25 1.25 {name=conn_1 dir=inout pinnumber=1}
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A 4 -5 0 5 270 360 {}
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P 4 5 -10 10 -30 10 -30 -10 -10 -10 -10 10 {}
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T {@#0:pinnumber} -13.75 -1.25 0 1 0.1 0.1 {}
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T {@name} -38.75 -23.75 0 0 0.2 0.2 {}
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