v {xschem version=3.4.4 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2024 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {type=connector
format="*connector(1,1) @pinlist"
tedax_format="footprint @name @footprint"
template="name=c1 footprint=connector(1,1)"}
V {}
S {}
E {}
B 5 -1.25 -1.25 1.25 1.25 {name=conn_1 dir=inout pinnumber=1}
A 4 -5 0 5 270 360 {}
P 4 5 -10 10 -30 10 -30 -10 -10 -10 -10 10 {}
T {@#0:pinnumber} -13.75 -1.25 0 1 0.1 0.1 {}
T {@name} -38.75 -23.75 0 0 0.2 0.2 {}