A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Schippers c627f21057 optimize previous fix, avod skipping lines after embedded symbol (embed_fd) 2020-09-24 17:46:58 +02:00
XSchemWin Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
doc add attributes "weight=bold", "slant=italic", "slant=oblique" on text objects for bold/italic/oblique texts, doc updates. 2020-09-23 18:15:26 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src optimize previous fix, avod skipping lines after embedded symbol (embed_fd) 2020-09-24 17:46:58 +02:00
tests Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
xschem_library optimize previous fix, avod skipping lines after embedded symbol (embed_fd) 2020-09-24 17:46:58 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse. Manual and instructions: http://repo.hu/projects/xschem/xschem_man/xschem_man.html