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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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schippes c5f412bdb7 symbol attribute @symname will display symbol name without extension as it used to be in earlier versions. @symname_ext will print full rootname of symbol. Some doc updates on symbol attributes 2020-08-12 11:31:42 +02:00
XSchemWin Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
doc symbol attribute @symname will display symbol name without extension as it used to be in earlier versions. @symname_ext will print full rootname of symbol. Some doc updates on symbol attributes 2020-08-12 11:31:42 +02:00
scconfig removed some dead code, remove_symbol() can remove i-th symbol, not only last one 2020-08-10 09:16:11 +02:00
src symbol attribute @symname will display symbol name without extension as it used to be in earlier versions. @symname_ext will print full rootname of symbol. Some doc updates on symbol attributes 2020-08-12 11:31:42 +02:00
tests Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
xschem_library symbol attribute @symname will display symbol name without extension as it used to be in earlier versions. @symname_ext will print full rootname of symbol. Some doc updates on symbol attributes 2020-08-12 11:31:42 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
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Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
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README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Add manual link 2020-08-08 16:04:20 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse. Manual and instructions: http://repo.hu/projects/xschem/xschem_man/xschem_man.html