luke
/
xschem
mirror of https://github.com/StefanSchippers/xschem.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
343 Commits 3 Branches 10 Tags 87 MiB
C 71.5%
Tcl 15.7%
Awk 8.2%
Roff 2%
Yacc 0.7%
Other 1.8%
Go to file
Stefan Frederik c3aad2fbfc remove dbg messages 2020-12-04 13:02:19 +01:00
XSchemWin added some comments 2020-11-26 04:01:11 +01:00
doc removed event_reporting feature 2020-11-29 03:27:45 +01:00
scconfig turn off dbg messages 2020-12-02 12:50:08 +01:00
src remove dbg messages 2020-12-04 13:02:19 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library remove dbg messages 2020-12-04 13:02:19 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS populating xschem git repo 2020-08-08 15:47:34 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog update Changelog 2020-12-01 17:13:46 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions