A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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Stefan Schippers b24c9ed763 fix an issue if "xschem ./sch_file.sch" is given on commandline, in this case load_file() will set current_dirname to /some/path/., this confuses abs_sym_path, so remove trailing /. in this case.		2020-10-26 02:31:47 +01:00
XSchemWin	according to answer from ngspice guys ngspice does not accept continuation lines for .title, .include and .lib statements, so break.awk will avoid breaking those lines. reversed default for tcl dim_background variable, so toggle colorscheme will work.	2020-10-23 01:19:03 +02:00
doc	"Delete files" menu command added	2020-10-24 23:46:19 +02:00
scconfig	"xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg)	2020-09-22 13:35:55 +02:00
src	fix an issue if "xschem ./sch_file.sch" is given on commandline, in this case load_file() will set current_dirname to /some/path/., this confuses abs_sym_path, so remove trailing /. in this case.	2020-10-26 02:31:47 +01:00
tests	better wire connecting bubble zoom scaling at different snap levels	2020-10-07 19:45:40 +02:00
xschem_library	sqwsource.sym: better labels, various fixes, comments and more debug messages in tcleval() stuff, some fixes (error checks) in "device_model" related model_name() function	2020-10-25 03:03:23 +01:00
.gitignore	changed .gitignore for specific xschem files	2020-08-08 23:25:43 +02:00
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Changelog	fix Browse button in edit symbol prop dialog	2020-09-15 14:15:43 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions