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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik aec7d02c4d tedax: do not generate __UNCONNECTED_PIN__%d names for unconnected instance pins in tedax netlist, do not highlight in red instances with unconected pins, still print ERC warning just in case designer forgot a connection 2022-01-11 14:40:43 +01:00
XSchemWin fix BadDrawable regression in free_rawfile(): after deleting data a draw() was called, but since this function is called also in exit handler all windows are already closed. Added digital waveforms and bussed signal display 2021-12-29 05:11:39 +01:00
doc doc updates 2022-01-11 12:17:15 +01:00
scconfig don`t try bring up the info ERC window if xschem is used in cli mode without X; filter out some events from graph event callback 2022-01-06 22:38:00 +01:00
src tedax: do not generate __UNCONNECTED_PIN__%d names for unconnected instance pins in tedax netlist, do not highlight in red instances with unconected pins, still print ERC warning just in case designer forgot a connection 2022-01-11 14:40:43 +01:00
tests cleanup in tabbed/multi-context code, remoevd redundant functions, more tests in xschemtest 2022-01-11 01:09:56 +01:00
xschem_library tedax: do not generate __UNCONNECTED_PIN__%d names for unconnected instance pins in tedax netlist, do not highlight in red instances with unconected pins, still print ERC warning just in case designer forgot a connection 2022-01-11 14:40:43 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog bump version to 3.0.0; prepare for 3.0.0 release 2021-09-11 07:53:11 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in scconfig test for dup2() availability 2021-10-25 01:53:00 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions