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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik ae0ffa926d set reasonable subdiv[xy] value when user switches from linear to log axis, as 8 subdivisions are used in log axes in 99.99% of the cases. 2022-08-08 12:37:44 +02:00
XSchemWin user selectable log X scale instead of assiming log X for AC analyses only 2022-08-05 00:57:03 +02:00
doc Button 1 Double click does edit object attributes 2022-07-31 09:06:10 +02:00
scconfig bump version to 3.1.0 (candidate #1) 2022-07-19 09:25:34 +02:00
src set reasonable subdiv[xy] value when user switches from linear to log axis, as 8 subdivisions are used in log axes in 99.99% of the cases. 2022-08-08 12:37:44 +02:00
tests update license info 2022-06-24 00:36:12 +02:00
xschem_library get_raw_value(): return plain value, no implicit log calculation if log scale on axis. Zoom full scale X and X axis pan: use 1st sweep X variable, do not assume spice sweep variable (idx==0) 2022-08-08 09:52:33 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions