A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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Stefan Frederik a7277acfda some more brace protected filenames in C tcl calls		2021-12-03 23:59:46 +01:00
XSchemWin	new find_inst_to_be_redrawn() implementation to recalculate area to be redrawn with/without show net names on symbol pins, simplified new_window() call in callback `x` command, code formatting in globals.c, added xschem get [xy]origin commands	2021-12-03 19:15:07 +01:00
doc	doc updates about menu text change	2021-12-01 15:03:10 +01:00
scconfig	old_winpath[] removed from globals, put as static string into callback(), fix ngspice::annotate netlist_dir fetching.	2021-11-23 23:20:10 +01:00
src	some more brace protected filenames in C tcl calls	2021-12-03 23:59:46 +01:00
tests	removed duplicate netlist_dir global var in C code, use tcl netlist_dir variable, some widgets now display on top of current schematic window instead of xschem`s master window (use [xschem get topwindow] instead of ".")	2021-11-23 17:02:36 +01:00
xschem_library	new find_inst_to_be_redrawn() implementation to recalculate area to be redrawn with/without show net names on symbol pins, simplified new_window() call in callback `x` command, code formatting in globals.c, added xschem get [xy]origin commands	2021-12-03 19:15:07 +01:00
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Changelog	bump version to 3.0.0; prepare for 3.0.0 release	2021-09-11 07:53:11 +02:00
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README_MacOS.md	added notes for MacOS 'Big Sur' builds.	2021-09-26 13:24:51 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions