51 lines
1.7 KiB
Plaintext
51 lines
1.7 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2023 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=logo
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template="name=l1 author=\\"Stefan Schippers\\" rev=1.0 lock=false"
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verilog_ignore=true
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vhdl_ignore=true
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spice_ignore=true
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tedax_ignore=true
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}
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V {}
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S {}
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E {}
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L 4 385 0 3430 0 {}
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L 4 0 0 65 0 {}
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L 4 3430 -2430 3430 0 {}
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L 4 0 -2430 3430 -2430 {}
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L 4 0 -2430 0 0 {}
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L 4 2110 -160 2110 0 {}
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L 4 2110 -160 3430 -160 {}
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L 4 2110 -80 3430 -80 {}
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L 4 2740 -80 2740 0 {}
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L 4 2740 -160 2740 -80 {}
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L 4 2450 -80 2450 0 {}
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P 5 13 165 -30 135 0 165 30 145 30 125 10 105 30 85 30 115 0 85 -30 105 -30 125 -10 145 -30 165 -30 {fill=true}
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T {SCHEM} 165 -25 0 0 1 1 {}
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T {@time_last_modified} 2750 -60 0 0 0.8 0.8 {}
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T {@author} 2120 -140 0 0 0.8 0.8 {}
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T {Page @page of @pages} 2120 -60 0 0 0.8 0.8 {}
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T {@title} 2750 -120 0 0 0.6 0.6 {vcenter=true}
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T {Rev. @rev} 2460 -60 0 0 0.8 0.8 {}
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