v {xschem version=3.4.4 file_version=1.2 * * This file is part of XSCHEM, * a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit * simulation. * Copyright (C) 1998-2023 Stefan Frederik Schippers * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA } G {} K {type=logo template="name=l1 author=\\"Stefan Schippers\\" rev=1.0 lock=false" verilog_ignore=true vhdl_ignore=true spice_ignore=true tedax_ignore=true } V {} S {} E {} L 4 385 0 3430 0 {} L 4 0 0 65 0 {} L 4 3430 -2430 3430 0 {} L 4 0 -2430 3430 -2430 {} L 4 0 -2430 0 0 {} L 4 2110 -160 2110 0 {} L 4 2110 -160 3430 -160 {} L 4 2110 -80 3430 -80 {} L 4 2740 -80 2740 0 {} L 4 2740 -160 2740 -80 {} L 4 2450 -80 2450 0 {} P 5 13 165 -30 135 0 165 30 145 30 125 10 105 30 85 30 115 0 85 -30 105 -30 125 -10 145 -30 165 -30 {fill=true} T {SCHEM} 165 -25 0 0 1 1 {} T {@time_last_modified} 2750 -60 0 0 0.8 0.8 {} T {@author} 2120 -140 0 0 0.8 0.8 {} T {Page @page of @pages} 2120 -60 0 0 0.8 0.8 {} T {@title} 2750 -120 0 0 0.6 0.6 {vcenter=true} T {Rev. @rev} 2460 -60 0 0 0.8 0.8 {}