luke
/
xschem
mirror of https://github.com/StefanSchippers/xschem.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
3,050 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
Other 1.7%
Go to file
Chayan Deb a184d38007
Merge branch 'StefanSchippers:master' into master 		2025-01-09 17:21:52 +05:30
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin updated greycnt.sch example 2024-12-18 14:01:50 +01:00
doc update docs on graphs y-zoom 2025-01-08 15:31:00 +01:00
scconfig xschem raw add: add optional sweep_var parameter 2024-12-09 00:00:27 +01:00
src Merge branch 'StefanSchippers:master' into master 2025-01-09 17:21:52 +05:30
tests update xschemtest expected netlist hashes 2024-12-23 11:15:36 +01:00
xschem_library optimization in plotting routines: skip unwanted datasets, if no dc simulation there is no need to detect sweep variable wraps 2025-01-08 13:27:07 +01:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog 2024-12-16 17:01:38 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile make uninstall: remove empty directories (share/xschem and share/doc/xschem); make command `xschem help` work also if running in src/ directory; use XSCHEM_SHAREDIR shell variable (if defined and directory existing), else set XCSCHEM_SHAREDIR to `pwd` if started from src/ dir, else set compile set XSCHEM_SHAREDIR. xschemrc can override this XSCHEM_SHAREDIR setting. 2025-01-05 01:29:04 +01:00
Makefile.conf.in remove check for libreadline (not used) 2024-11-13 01:35:24 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove check for libreadline (not used) 2024-11-13 01:35:24 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions